# DDR4 layer assignment **URL:** \ **Category:** Design and Layout\ **Created:** [January 14, 2026, 6:15pm UTC](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804 "2026-01-14T18:15:16Z")\ **Posts on this page:** 19\ **Page:** 1
**Author:** ![bruce\_northrop](https://avatars.discourse-cdn.com/v4/letter/b/a88e57/32.png) [@bruce\_northrop](https://sierraconnect.protoexpress.com/u/bruce_northrop)\ **Post date:** [January 14, 2026, 6:15pm UTC](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804/1 "2026-01-14T18:15:16Z")
Hello - Looking for some guidance on layer assignment for data lines on a DDR4 chip set. I’ve been all over the internet and found too much info. Can anyone provide something concise. I’ve also rerouted this a couple times and falling a bit behind. I have screenshots of the chips I’m using if that would help. Thanks, Bruce ---
**Author:** ![lucy.sierracircuits](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/lucy.sierracircuits/32/8_2.png) [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Post date:** [January 16, 2026, 12:09am UTC](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804/2 "2026-01-16T00:09:08Z")
Hi Bruce, could you share the screenshots for our team to look at them? ---
**Author:** ![timothy.phillips](https://avatars.discourse-cdn.com/v4/letter/t/d78d45/32.png) [@timothy.phillips](https://sierraconnect.protoexpress.com/u/timothy.phillips)\ **Post date:** [January 20, 2026, 1:51pm UTC](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804/3 "2026-01-20T13:51:23Z")
The issue with trying to provide a specific response is that stackup is highly dependent on IC packaging, technologies being used (like HDI or not), and what else you need to connect to the MCU besides the DDR related nets. I personally have only done one DDR4 layout. Due to my particular restrictions, I could not route signals on the surface and I needed 3 internal signal layers to route everything out (plus additional PWR support). I included GND layers between each signal layers and also included a dedicated multi voltage split PWR layer. I can see depending on the situation, a user might need more that one dedicated PWR layer. In many cases, the MCU vendor has a eval board or hardware design guide that can be used to help guide you. You might need to ask for this information as it is considered restricted IP and they do not always have it openly accessable for download. As a side note, the Sierra stackup calculator can also help you try and determine a proposed stackup. Select “I have a complex BGA” option. ---
**Author:** ![bruce\_northrop](https://avatars.discourse-cdn.com/v4/letter/b/a88e57/32.png) [@bruce\_northrop](https://sierraconnect.protoexpress.com/u/bruce_northrop)\ **Post date:** [January 21, 2026, 4:59pm UTC](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804/4 "2026-01-21T16:59:57Z")
Hello Lucy, yes, I can post screenshots. I’ve had to do some re-routing, so it will be a few days before I have things cleaned up. Stay tuned… Thanks. ---
**Author:** ![bruce\_northrop](https://avatars.discourse-cdn.com/v4/letter/b/a88e57/32.png) [@bruce\_northrop](https://sierraconnect.protoexpress.com/u/bruce_northrop)\ **Post date:** [January 21, 2026, 5:04pm UTC](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804/5 "2026-01-21T17:04:13Z")
Tim, are you the same Tim from Altium? I have figured out a path forward. Getting everything routed and length matched is the next challenge. I should be posting screenshots here soon if you want to check those out. Thanks. ---
**Author:** ![timothy.phillips](https://avatars.discourse-cdn.com/v4/letter/t/d78d45/32.png) [@timothy.phillips](https://sierraconnect.protoexpress.com/u/timothy.phillips)\ **Post date:** [January 21, 2026, 5:32pm UTC](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804/6 "2026-01-21T17:32:05Z")
I use Altium and I post on the Altium forum, but I am not Altium staff. ---
**Author:** ![lucy.sierracircuits](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/lucy.sierracircuits/32/8_2.png) [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Post date:** [January 21, 2026, 6:38pm UTC](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804/7 "2026-01-21T18:38:12Z")
Thanks for mention our Stackup Designer! It’s a great tool and we improved it recently, adding more options for different requirements: [https://www.protoexpress.com/tools/pcb-stackup-designer/](https://www.protoexpress.com/tools/pcb-stackup-designer/) ---
**Author:** ![bruce\_northrop](https://avatars.discourse-cdn.com/v4/letter/b/a88e57/32.png) [@bruce\_northrop](https://sierraconnect.protoexpress.com/u/bruce_northrop)\ **Post date:** [March 4, 2026, 3:34pm UTC](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804/8 "2026-03-04T15:34:43Z")
Hello Lucy - I have this finished and was going to upload some screenshots, but it says I can’t upload more than one. I have 8. Any suggestions, or just do one at a time? Thanks, Bruce ---
**Author:** ![lucy.sierracircuits](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/lucy.sierracircuits/32/8_2.png) [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Post date:** [March 5, 2026, 5:55pm UTC](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804/9 "2026-03-05T17:55:44Z")
I changed the settings. You should be good to upload now. ---
**Author:** ![bruce\_northrop](https://avatars.discourse-cdn.com/v4/letter/b/a88e57/32.png) [@bruce\_northrop](https://sierraconnect.protoexpress.com/u/bruce_northrop)\ **Post date:** [March 10, 2026, 5:45pm UTC](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804/10 "2026-03-10T17:45:34Z")
I’m still getting the same message, “An error occurred: Sorry, new users can only put one embedded media item in a post.” ---
**Author:** ![lucy.sierracircuits](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/lucy.sierracircuits/32/8_2.png) [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Post date:** [March 10, 2026, 6:03pm UTC](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804/11 "2026-03-10T18:03:32Z")
Hmm sorry about that. While I’m working on fixing this, I edited your profile to a level 1 user. So you should be good now… I hope. Fingers crossed! ---
**Author:** ![bruce\_northrop](https://avatars.discourse-cdn.com/v4/letter/b/a88e57/32.png) [@bruce\_northrop](https://sierraconnect.protoexpress.com/u/bruce_northrop)\ **Post date:** [March 10, 2026, 6:22pm UTC](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804/12 "2026-03-10T18:22:58Z")
Thanks Lucy! Attached are screen shots of the DDR layers. There are 4 pairs of RAM’s routed from a large FPGA. Address lines are layers 3, 5, 7, 9 for the 4 pairs. Data lines are divided into groups of 8 and routed on layers 16, 18, 20 and 22. GND planes in between all. Length matched for appropriate group. The biggest issue I think I have is trace to trace spacing which is tighter than recommended. Not sure if this is a showstopper or not. Any input would be greatly appreciated. ![DDR4 L3](https://global.discourse-cdn.com/sierraconnect/original/1X/274f068e123d638efba6f9d14f94af732577565d.jpeg) ![DDR4 L5](https://global.discourse-cdn.com/sierraconnect/original/1X/4f4e0820f489b17d1ff6e05f8bba482d36e51cf7.png) ![DDR4 L7](https://global.discourse-cdn.com/sierraconnect/original/1X/be5314cefd96b9eb7df2013aabc3418684bde70a.png) ![DDR4 L9](https://global.discourse-cdn.com/sierraconnect/original/1X/d4f0e99f9adece8e481063e9b35f4c6a51ef5b4f.jpeg) ![DDR4 L16](https://global.discourse-cdn.com/sierraconnect/original/1X/abffc5cef7c93aef4a18b530cfb8e7497a3547b3.png) ![DDR4 L18](https://global.discourse-cdn.com/sierraconnect/original/1X/ff1b33d97b33936c3ce29a65224c4a0080fa6eac.png) ![DDR4 L20](https://global.discourse-cdn.com/sierraconnect/original/1X/7841a50ced9a67beb8d46cc48efaffd0efd0fcd3.png) ![DDR4 L22](https://global.discourse-cdn.com/sierraconnect/original/1X/b2f5ec2ca2556365a0ee17c6018e40a4cb31bcd6.png) ---
**Author:** ![bruce\_northrop](https://avatars.discourse-cdn.com/v4/letter/b/a88e57/32.png) [@bruce\_northrop](https://sierraconnect.protoexpress.com/u/bruce_northrop)\ **Post date:** [March 10, 2026, 6:23pm UTC](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804/13 "2026-03-10T18:23:43Z")
Yup, works now. Thanks Lucy! ---
**Author:** ![lucy.sierracircuits](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/lucy.sierracircuits/32/8_2.png) [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Post date:** [March 10, 2026, 6:40pm UTC](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804/14 "2026-03-10T18:40:39Z")
Ah great! Thanks for your patience. 🙂 ---
**Author:** ![olddsgnr](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/olddsgnr/32/638_2.png) [@olddsgnr](https://sierraconnect.protoexpress.com/u/olddsgnr)\ **Post date:** [March 12, 2026, 1:12am UTC](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804/15 "2026-03-12T01:12:23Z")
Well, what was the recommended spacing vs. what you routed with? Did your manufacturer confirm the your needed impedance compared to their capabilities? That is key! Also, have you ever routed to timing constraints instead of just length matching? Where the built in analysis looks at your physical configuration? If you have the right tools you could get better dialed in. ---
**Author:** ![bruce\_northrop](https://avatars.discourse-cdn.com/v4/letter/b/a88e57/32.png) [@bruce\_northrop](https://sierraconnect.protoexpress.com/u/bruce_northrop)\ **Post date:** [March 12, 2026, 7:14pm UTC](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804/16 "2026-03-12T19:14:14Z")
Yes, we have a stack-up from our board supplier with required impedance models. Everything is routed to that spec. The spacing I refer to that might cause me some issue is a rule of thumb from the internet saying that trace to trace should be 3x trace width. I don’t have that much room, and maybe that’s all it is a rule of thumb. ---
**Author:** ![olddsgnr](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/olddsgnr/32/638_2.png) [@olddsgnr](https://sierraconnect.protoexpress.com/u/olddsgnr)\ **Post date:** [March 13, 2026, 4:14am UTC](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804/17 "2026-03-13T04:14:41Z")
Yup. Rules of thumb are directly dependent on the size of your thumb. It’s sort of like saying… it depends. But o’ luck with your design. ---
**Author:** ![aryanbrb](https://avatars.discourse-cdn.com/v4/letter/a/e0b2c6/32.png) [@aryanbrb](https://sierraconnect.protoexpress.com/u/aryanbrb)\ **Post date:** [March 13, 2026, 9:22am UTC](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804/18 "2026-03-13T09:22:10Z")
It’s hard to tell from screenshot but whenever you do fine tuning of single ended signals your same net trace-to-trace clearance plays a good role in determining according or trombone radius. I hope you have taken care of that. ---
**Author:** ![bruce\_northrop](https://avatars.discourse-cdn.com/v4/letter/b/a88e57/32.png) [@bruce\_northrop](https://sierraconnect.protoexpress.com/u/bruce_northrop)\ **Post date:** [March 13, 2026, 12:50pm UTC](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804/19 "2026-03-13T12:50:03Z")
Yes, I used (hopefully) proper trombone clearances. Thanks.