# Clarifying My Understanding of DDR3 Signal Routing **URL:** \ **Category:** General\ **Tags:** high-speed\ **Created:** [May 6, 2025, 4:48am UTC](https://sierraconnect.protoexpress.com/t/clarifying-my-understanding-of-ddr3-signal-routing/3152 "2025-05-06T04:48:55Z")\ **Posts on this page:** 1\ **Showing post:** 8
**Author:** ![timothy.phillips](https://avatars.discourse-cdn.com/v4/letter/t/d78d45/32.png) [@timothy.phillips](https://sierraconnect.protoexpress.com/u/timothy.phillips)\ **Post date:** [May 8, 2025, 12:58pm UTC](https://sierraconnect.protoexpress.com/t/clarifying-my-understanding-of-ddr3-signal-routing/3152/8 "2025-05-08T12:58:06Z")
Keep in mind that there usually is more than one potential method to route DDR critical signals. Many times, the processor manufacturer has guidelines that explains the options and recommendations. Note that these guides many times are hidden behind security so you usually need to request access. Beyond that, keep in mind that length matching generally is better if you are matching delay length/time instead of physical length. Where this becomes really important is when you route some nets on outer layers, but other nets for the same group on inner layers. Delay time is different between inner and outer layers and this needs to be compensated for. This is why many recommendations suggest routing all of a group on a single layer in order for physical variences to be applied equally across the complete group. Do not forget that vias also have “length” so make sure your layout tool acounts for that based on signal path, not just overall via length. Another item to note is that within the processor, each net has internal delay that is unique to the internal configuration. These delays also should be figured into the overall delay calculations in order to increase the accuracy of length matching. It is best to use solid GND reference layers adjacient to critical signals. Avoid PWR layers for returns and if done anyway, do NOT route over splits/voids and be sure the signals are adjacent to the correct voltage that powers those signals. I highly recommend Beeker’s “Billion Dollar Mistake” seminar. > [@Seminar: The Billion-Dollar Mistake by Daniel Beeker](https://sierraconnect.protoexpress.com/t/seminar-the-billion-dollar-mistake-by-daniel-beeker/3127): > > Join us on June 24-25th for a two-day EMC class by @daniel.beeker! Seminar agenda: The billion dollar mistake: Changing the status quo Electromagnetic fields for normal folks: Show me the pictures and hold the equations, please! Effective PCB design: Techniques to improve performance Novel power distribution system design Feeding the beast: Consumption-based PCB design Stacking the deck: Maximizing the PCB layer design for signal integrity and EMC performance HDI via design: Planning the energ… One last thought. PCB fabrication has tolerances so the best bet is to length match nets as tight as possible instead of to the largest tolerance allowed by guides. You do NOT want to design at the edge of length tolerances, only to find that PCB fabrication tolerances (which are out of the designer’s control) push the result over the limit. --- _[View the full topic](https://sierraconnect.protoexpress.com/t/clarifying-my-understanding-of-ddr3-signal-routing/3152)._