# Best practices for using ground pours on 4-layer PCBs with internal planes **URL:** \ **Category:** Design and Layout\ **Tags:** grounding\ **Created:** [October 8, 2025, 3:32pm UTC](https://sierraconnect.protoexpress.com/t/best-practices-for-using-ground-pours-on-4-layer-pcbs-with-internal-planes/3624 "2025-10-08T15:32:59Z")\ **Posts on this page:** 4\ **Page:** 1
**Author:** ![Sophia](https://avatars.discourse-cdn.com/v4/letter/s/b2d939/32.png) [@Sophia](https://sierraconnect.protoexpress.com/u/Sophia)\ **Post date:** [October 8, 2025, 3:32pm UTC](https://sierraconnect.protoexpress.com/t/best-practices-for-using-ground-pours-on-4-layer-pcbs-with-internal-planes/3624/1 "2025-10-08T15:32:59Z")
I’m designing a 4-layer PCB where the two inner layers are solid ground planes, and the outer layers carry signals. Since I’ve always added ground pours on 2-layer designs, I’m wondering should I still add ground pours with stitching vias on the outer layers when internal ground planes are already present? ---
**Author:** ![timothy.phillips](https://avatars.discourse-cdn.com/v4/letter/t/d78d45/32.png) [@timothy.phillips](https://sierraconnect.protoexpress.com/u/timothy.phillips)\ **Post date:** [October 8, 2025, 7:54pm UTC](https://sierraconnect.protoexpress.com/t/best-practices-for-using-ground-pours-on-4-layer-pcbs-with-internal-planes/3624/2 "2025-10-08T19:54:37Z")
Read this thread… > [@Should empty spaces on a 4-layer PCB be filled with ground?](https://sierraconnect.protoexpress.com/t/should-empty-spaces-on-a-4-layer-pcb-be-filled-with-ground/2858): > > For a 4-layer PCB with the following stack-up: Layer 1: High-speed signal Layer 2: Dedicated ground plane Layer 3: Power plane (5V, 3.3V, 1.8V) Layer 4: Normal-speed signal On single/double-layer boards, the usual practice is to fill all unused space with ground. Since a dedicated ground plane already exists on Layer 2, is it still beneficial to fill the empty spaces on Layer 1 and Layer 4 with a ground pour? Would this improve signal integrity, or could it introduce potential issues? ---
**Author:** ![myrtlee](https://avatars.discourse-cdn.com/v4/letter/m/3bc359/32.png) [@myrtlee](https://sierraconnect.protoexpress.com/u/myrtlee)\ **Post date:** [October 9, 2025, 2:08pm UTC](https://sierraconnect.protoexpress.com/t/best-practices-for-using-ground-pours-on-4-layer-pcbs-with-internal-planes/3624/3 "2025-10-09T14:08:36Z")
Your 4-layer stackup (signal–ground–ground–signal) is excellent, each signal layer references a solid adjacent ground plane, giving you a low-impedance return path for current. Keep in mind that for digital designs, signal integrity depends more on edge rates than on clock frequency. Modern ICs with fast rise and fall times can generate high-frequency components, even at relatively low clock speeds, so maintaining continuous return paths remains important. You generally don’t need ground pours on the outer layers in this configuration. However, adding them can still offer some benefits. They reduce copper etching during fabrication and can slightly improve thermal performance. As long as your ground vias already connect efficiently to the internal planes and your design isn’t pushing into high-speed territory, extra stitching vias aren’t required. That said, a modest number won’t hurt, provided it doesn’t inflate fabrication costs. ---
**Author:** ![jerrysaitter](https://avatars.discourse-cdn.com/v4/letter/j/c68b51/32.png) [@jerrysaitter](https://sierraconnect.protoexpress.com/u/jerrysaitter)\ **Post date:** [October 10, 2025, 12:58pm UTC](https://sierraconnect.protoexpress.com/t/best-practices-for-using-ground-pours-on-4-layer-pcbs-with-internal-planes/3624/4 "2025-10-10T12:58:08Z")
One additional point worth mentioning is to place ground return vias close to any signal or power vias when signals transition between layers. This helps maintain a consistent return path in the vertical direction, ensuring the signal always has a nearby reference plane and minimizing loop inductance.