# Ask Me Anything with Kenneth Wyatt **URL:** \ **Category:** Ask Me Anything\ **Tags:** emc, ama\ **Created:** [January 4, 2024, 5:58pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807 "2024-01-04T17:58:46Z")\ **Posts on this page:** 20\ **Page:** 1
**Author:** ![lucy.sierracircuits](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/lucy.sierracircuits/32/8_2.png) [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Post date:** [January 4, 2024, 5:58pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807/1 "2024-01-04T17:58:46Z")
> **Ask Me Anything with Kenneth Wyatt** > > **Starts:** January 10, 2024, 1:00pm (America/Los\_Angeles)\ > **Ends:** January 10, 2024, 2:00pm (America/Los\_Angeles) **Kenneth Wyatt** will answer your **EMC** questions here! ---
**Author:** ![Pooja\_Mitra](https://avatars.discourse-cdn.com/v4/letter/p/ce73a5/32.png) [@Pooja\_Mitra](https://sierraconnect.protoexpress.com/u/Pooja_Mitra)\ **Post date:** [January 9, 2024, 9:28am UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807/3 "2024-01-09T09:28:12Z")
Does trace shielding block EM radiation effectively? Can you recommend the 2 best methods of shielding? ---
**Author:** ![Mohamed\_Faheemuddin](https://avatars.discourse-cdn.com/v4/letter/m/4da419/32.png) [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Post date:** [January 9, 2024, 9:28am UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807/4 "2024-01-09T09:28:54Z")
Are there any specific tools to test for EMC of a circuit board? ---
**Author:** ![Pooja\_Mitra](https://avatars.discourse-cdn.com/v4/letter/p/ce73a5/32.png) [@Pooja\_Mitra](https://sierraconnect.protoexpress.com/u/Pooja_Mitra)\ **Post date:** [January 9, 2024, 9:29am UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807/5 "2024-01-09T09:29:15Z")
I generally implement via stitching to ensure grounding in high-speed designs. Which is the best optimal via-to-via spacing to manage EMI effectively? ---
**Author:** ![Mohamed\_Faheemuddin](https://avatars.discourse-cdn.com/v4/letter/m/4da419/32.png) [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Post date:** [January 9, 2024, 9:29am UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807/6 "2024-01-09T09:29:58Z")
What is the effective strategy to suppress EM radiation: placing multiple decoupling capacitors of the same value or various capacitors with different values? ---
**Author:** ![milan](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/milan/32/10_2.png) [@milan](https://sierraconnect.protoexpress.com/u/milan)\ **Post date:** [January 9, 2024, 9:32am UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807/7 "2024-01-09T09:32:37Z")
What are your strategies to avoid EMC issues in mixed-signal PCBs? ---
**Author:** ![milan](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/milan/32/10_2.png) [@milan](https://sierraconnect.protoexpress.com/u/milan)\ **Post date:** [January 9, 2024, 9:33am UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807/8 "2024-01-09T09:33:22Z")
Are there any specific design considerations to ensure the EMC of 5G and IoT PCBs? ---
**Author:** ![PoulomiG](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/poulomig/32/288_2.png) [@PoulomiG](https://sierraconnect.protoexpress.com/u/PoulomiG)\ **Post date:** [January 9, 2024, 9:39am UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807/9 "2024-01-09T09:39:38Z")
How can we prevent EM radiation from the switching power supply? ---
**Author:** ![PoulomiG](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/poulomig/32/288_2.png) [@PoulomiG](https://sierraconnect.protoexpress.com/u/PoulomiG)\ **Post date:** [January 9, 2024, 9:40am UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807/10 "2024-01-09T09:40:07Z")
What kind of filter should we use to avoid EMI in clock circuits and high-speed components? How should we position the filter near the component? ---
**Author:** ![Jane](https://avatars.discourse-cdn.com/v4/letter/j/ecb155/32.png) [@Jane](https://sierraconnect.protoexpress.com/u/Jane)\ **Post date:** [January 9, 2024, 9:41am UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807/11 "2024-01-09T09:41:19Z")
To split or not to split: What is your opinion on spitting ground planes? Is It true that it can cause impedance variations? ---
**Author:** ![Emma](https://avatars.discourse-cdn.com/v4/letter/e/57b2e6/32.png) [@Emma](https://sierraconnect.protoexpress.com/u/Emma)\ **Post date:** [January 9, 2024, 9:45am UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807/12 "2024-01-09T09:45:34Z")
I saw that the placement of high-speed circuits close to the GND plane and low-speed circuits to the power plane was recommended. Do you back this up? Would that truly be necessary for a solid return path? ---
**Author:** ![ken](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/ken/32/93_2.png) [@ken](https://sierraconnect.protoexpress.com/u/ken)\ **Post date:** [January 10, 2024, 8:55pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807/13 "2024-01-10T20:55:18Z")
Sorry, this question is not within the scope of EMC. ---
**Author:** ![ken](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/ken/32/93_2.png) [@ken](https://sierraconnect.protoexpress.com/u/ken)\ **Post date:** [January 10, 2024, 8:56pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807/14 "2024-01-10T20:56:57Z")
Trace shielding can be implemented two way; through use of stripline and by using local shields over sections of the PC board. See: [Local Shield Options for Wireless/RF Products | Signal Integrity Journal](https://www.signalintegrityjournal.com/blogs/17-practical-emc/post/2805-local-shield-options-for-wireless-rf-products) ---
**Author:** ![ken](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/ken/32/93_2.png) [@ken](https://sierraconnect.protoexpress.com/u/ken)\ **Post date:** [January 10, 2024, 9:03pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807/15 "2024-01-10T21:03:17Z")
I’ve written extensively on PC board characterizations using simple tools, such as near field probes. Please refer to the following: 1. My “EMC Troubleshooting Trilogy” books on Amazon ([Amazon.com: Kenneth Wyatt: books, biography, latest update](https://www.amazon.com/stores/Kenneth-Wyatt/author/B00SNQ1LJ2)) 2. Assembling an EMC troubleshooting kit ([Assembling an EMC Troubleshooting Kit: Radiated Emissions | Signal Integrity Journal](https://www.signalintegrityjournal.com/blogs/17-practical-emc/post/2387-assembling-an-emc-troubleshooting-kit-radiated-emissions)) 3. Tektronix application note they kindly had me write ([Step by Step EMI Troubleshooting with 4, 5 and 6 Series MSO Oscilloscopes | Tektronix](https://www.tek.com/en/documents/application-note/step-by-step-emi-troubleshooting-with-4-5-and-6-series-msos)) ---
**Author:** ![ken](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/ken/32/93_2.png) [@ken](https://sierraconnect.protoexpress.com/u/ken)\ **Post date:** [January 10, 2024, 9:05pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807/16 "2024-01-10T21:05:27Z")
For best results via-to-via stitching should be 1/20th wavelength for the highest frequency expected. Generally, this is every 2 cm for 20 dB shielding at 1 GHz. Typically, I recommend a via every 5mm. ---
**Author:** ![ken](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/ken/32/93_2.png) [@ken](https://sierraconnect.protoexpress.com/u/ken)\ **Post date:** [January 10, 2024, 9:07pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807/17 "2024-01-10T21:07:26Z")
Use the same values. See Dr. Eric Bogatin’s article, The Myth of Three Capacitors, here ([The Myth of Three Capacitor Values | 2020-03-03 | Signal Integrity Journal](https://www.signalintegrityjournal.com/articles/1589-the-myth-of-three-capacitor-values)) ---
**Author:** ![ken](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/ken/32/93_2.png) [@ken](https://sierraconnect.protoexpress.com/u/ken)\ **Post date:** [January 10, 2024, 9:11pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807/18 "2024-01-10T21:11:09Z")
(1) First, understand how digital signals propagate in PC boards. (2) Use a solid return plane! (3) Another great technique is to use the concept of partitioning noisy and quiet circuits. See my PC board design for low EMI series starting with Part 1 here ([Design PCBs for EMI, part 1: How signals move - EDN](https://www.edn.com/design-pcbs-for-emi-part-1-how-signals-move/)) ---
**Author:** ![ken](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/ken/32/93_2.png) [@ken](https://sierraconnect.protoexpress.com/u/ken)\ **Post date:** [January 10, 2024, 9:15pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807/19 "2024-01-10T21:15:17Z")
Besides the design of the PC board for low EMI cited previously, I find that on-board DC-DC converters create enough broadband EMI that it affects the receiver sensitivity in wireless and cellular modules. See: A Three-Step Process for Characterizing Self-Generated Interference for Wireless or IoT Products [A Three-Step Process for Characterizing Self-Generated Interference for Wireless or IoT Products | Signal Integrity Journal](https://www.signalintegrityjournal.com/blogs/17-practical-emc/post/3281-a-three-step-process-for-characterizing-self-generated-interference-for-wireless-or-iot-products)) Mitigating Self-Generated Interference for Wireless or IoT Products ([Mitigating Self-Generated Interference for Wireless or IoT Products | Signal Integrity Journal](https://www.signalintegrityjournal.com/blogs/17-practical-emc/post/3350-mitigating-self-generated-interference-for-wireless-or-iot-products)) ---
**Author:** ![ken](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/ken/32/93_2.png) [@ken](https://sierraconnect.protoexpress.com/u/ken)\ **Post date:** [January 10, 2024, 9:19pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807/20 "2024-01-10T21:19:55Z")
This is a broad topic. I’ve written on minimizing on-board DC-DC converter EMI, see Ten Tips to Minimize EMI from On-Board DC-DC Converters ([Ten Tips to Minimize EMI from On-Board DC-DC Converters | Interference Technology](https://interferencetechnology.com/ten-tips-to-minimize-emi-from-on-board-dc-dc-converters/)) If you’re referring to off-line (AC line) converters, then ensure the PC board includes a solid return plane as one layer (usually layer 2). Make sure any line filters are located right at the AC line ingress. ---
**Author:** ![ken](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/ken/32/93_2.png) [@ken](https://sierraconnect.protoexpress.com/u/ken)\ **Post date:** [January 10, 2024, 9:22pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807/21 "2024-01-10T21:22:03Z")
The best and simplest is to insert a 1k resistor in series with the clock trace. This, and the parasitic capacitance of the board will help roll off the rise/fall times of the clock. You should also minimize the length of the clock trace and ensure it does not run along board edges or near I/O connectors. [Next page](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-kenneth-wyatt/807.md?page=2)