# Ask Me Anything about KiCad 8

**URL:** https://sierraconnect.protoexpress.com/t/ask-me-anything-about-kicad-8/1787
**Category:** Ask Me Anything
**Tags:** kicad
**Created:** [September 4, 2024, 12:38am UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-about-kicad-8/1787 "2024-09-04T00:38:01Z")
**Posts on this page:** 14
**Page:** 1

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### Author: ![lucy.sierracircuits](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/lucy.sierracircuits/32/8_2.png) [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)
#### Post date: [September 4, 2024, 12:38am UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-about-kicad-8/1787/1 "2024-09-04T00:38:01Z")

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Join our next Ask Me Anything about KiCad 8 where you can ask us questions on:

- Diff pair routing
- Custom footprints
- Via placement
- And much more!

💬 **Question submission window:** Through September 11th

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### Author: ![nikh](https://avatars.discourse-cdn.com/v4/letter/n/6a8cbe/32.png) [@nikh](https://sierraconnect.protoexpress.com/u/nikh)
#### Post date: [September 9, 2024, 4:08am UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-about-kicad-8/1787/2 "2024-09-09T04:08:34Z")

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I’m currently using KICAD 7. I’ve created my own library with around 30 parts, including schematic symbols and footprints. Will I lose my library if I upgrade?

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### Author: ![Fen](https://avatars.discourse-cdn.com/v4/letter/f/b487fb/32.png) [@Fen](https://sierraconnect.protoexpress.com/u/Fen)
#### Post date: [September 9, 2024, 11:38pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-about-kicad-8/1787/3 "2024-09-09T23:38:42Z")

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Can KiCAD 8’s 3D Viewer accurately simulate multi layer PCBs with blind and buried vias for manufacturing checks?

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### Author: ![George](https://avatars.discourse-cdn.com/v4/letter/g/71e660/32.png) [@George](https://sierraconnect.protoexpress.com/u/George)
#### Post date: [September 10, 2024, 4:56am UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-about-kicad-8/1787/4 "2024-09-10T04:56:31Z")

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I’m not a Kicad user (yet) but wanted to know about trace length tuning for high speed SI? How does it comopare with Altium? Is it user-friendly and accurate?

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### Author: ![Madison](https://avatars.discourse-cdn.com/v4/letter/m/db5fbb/32.png) [@Madison](https://sierraconnect.protoexpress.com/u/Madison)
#### Post date: [September 10, 2024, 5:06am UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-about-kicad-8/1787/5 "2024-09-10T05:06:49Z")

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Can you share more info on the design block feature in KiCAD 8 and some best practices on how to use it for complex circuits? and will there be some changes regarding that with Kicad 9?

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### Author: ![gigio](https://avatars.discourse-cdn.com/v4/letter/g/839c29/32.png) [@gigio](https://sierraconnect.protoexpress.com/u/gigio)
#### Post date: [September 10, 2024, 3:36pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-about-kicad-8/1787/6 "2024-09-10T15:36:41Z")

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In board setup, default settings are provided for length matching rules but that acts like a common rule setting for every length matching group on all the layers. Suppose there are multiple group of signals having different trace width on different layers, is it possible to set specific rule to each group of signals?

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### Author: ![Timmann17](https://avatars.discourse-cdn.com/v4/letter/t/d07c76/32.png) [@Timmann17](https://sierraconnect.protoexpress.com/u/Timmann17)
#### Post date: [September 10, 2024, 6:16pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-about-kicad-8/1787/7 "2024-09-10T18:16:32Z")

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Is it possible to add drill chart in fab details in kicad V8, if yes how to add it?

 ![image](https://global.discourse-cdn.com/sierraconnect/original/1X/60cc8eedaf26c242d86012e507caa97eca3f037d.png)

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### Author: ![seth](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/seth/32/408_2.png) [@seth](https://sierraconnect.protoexpress.com/u/seth)
#### Post date: [September 11, 2024, 4:54pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-about-kicad-8/1787/8 "2024-09-11T16:54:34Z")

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No. Your library will not be overwritten as long as it is not saved in the global KiCad libraries. The global KiCad libraries are linked to each version and so will be uninstalled when the version associated with them is uninstalled.

We currently install the KiCad libraries as read only on Windows to prevent this from happening by accident. The libraries are inside the KiCad bundle for MacOS and installed to a system directory for Linux. As long as you are keeping your personal libraries in your home folder (which is the default), upgrading will not affect them

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### Author: ![seth](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/seth/32/408_2.png) [@seth](https://sierraconnect.protoexpress.com/u/seth)
#### Post date: [September 11, 2024, 4:57pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-about-kicad-8/1787/9 "2024-09-11T16:57:48Z")

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Yes, blind/buried vias are properly represented in the 3d viewer

 ![image](https://global.discourse-cdn.com/sierraconnect/original/1X/00be018b70d4cdacdc2325c5e557db6217ffce11.png)

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<div class="post-metadata">

### Author: ![seth](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/seth/32/408_2.png) [@seth](https://sierraconnect.protoexpress.com/u/seth)
#### Post date: [September 11, 2024, 4:59pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-about-kicad-8/1787/10 "2024-09-11T16:59:47Z")

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As a completely impartial KiCad developer, I think that trace length tuning in KiCad is great! 😉

In seriousness, our tuning tools are very accurate for length tuning and easy to adjust. Altium does a better job with timing tuning at the moment but we’re working on that.

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### Author: ![seth](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/seth/32/408_2.png) [@seth](https://sierraconnect.protoexpress.com/u/seth)
#### Post date: [September 11, 2024, 5:37pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-about-kicad-8/1787/11 "2024-09-11T17:37:49Z")

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Yes, if you would like to define different constraints that take other factors into account than just the net name, you can create them using custom rules.

We have a number of custom rule examples for doing this in our documentation at [PCB Editor | 8.0 | English | Documentation | KiCad](https://docs.kicad.org/8.0/en/pcbnew/pcbnew.html#custom_design_rules)

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<div class="post-metadata">

### Author: ![seth](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/seth/32/408_2.png) [@seth](https://sierraconnect.protoexpress.com/u/seth)
#### Post date: [September 11, 2024, 5:48pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-about-kicad-8/1787/12 "2024-09-11T17:48:40Z")

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Yes, you can do this.

## Step 1: Export the drill map to SVG:

1. Open Plot dialog
2. Click Generate Drill Files
3. Select “Map file format” **SVG**
4. Click Generate Map File

 ![image](https://global.discourse-cdn.com/sierraconnect/original/1X/bf81363d452630aac936f7666aba6517d2062364.png)

## Step 2: Import SVG file

1. Import Graphics

 ![image](https://global.discourse-cdn.com/sierraconnect/original/1X/28a1963c57b2845a80043e98e1723ecec0be9aac.png)

1. Select the file and layer of F.Fab.
2. Make sure that “Fix discontinuities” is unchecked and “Group imported items” is checked.  
 ![image](https://global.discourse-cdn.com/sierraconnect/original/1X/f78d898fb6c41b8d01798823bec22f433f2768ec.png)

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<div class="post-metadata">

### Author: ![seth](https://sea2.discourse-cdn.com/sierraconnect/user_avatar/sierraconnect.protoexpress.com/seth/32/408_2.png) [@seth](https://sierraconnect.protoexpress.com/u/seth)
#### Post date: [September 11, 2024, 5:51pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-about-kicad-8/1787/13 "2024-09-11T17:51:13Z")

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The design blocks feature was just added this past week into the development branch of what will become KiCad 9. It will not be available in KiCad 8.

This feature is still pretty new and will be fully documented in the KiCad docs prior to release.

It will allow the designer to have a standard set of designs/parts that they can place on existing schematics. This is meant to make reusable designs easier and facilitate sharing of design elements.

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<div class="post-metadata">

### Author: ![nikh](https://avatars.discourse-cdn.com/v4/letter/n/6a8cbe/32.png) [@nikh](https://sierraconnect.protoexpress.com/u/nikh)
#### Post date: [September 13, 2024, 8:51pm UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-about-kicad-8/1787/14 "2024-09-13T20:51:12Z")

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Thanks!
