# Latest **URL:** https://sierraconnect.protoexpress.com/latest.md?page=6 [Latest](https://sierraconnect.protoexpress.com/latest.md) · [Categories](https://sierraconnect.protoexpress.com/categories.md) · [Tags](https://sierraconnect.protoexpress.com/tags.md) **Page:** 7 --- ## [Why consumer power adapters & small appliances often use single-sided PCBs](https://sierraconnect.protoexpress.com/t/why-consumer-power-adapters-small-appliances-often-use-single-sided-pcbs/3906)
**Author:** [@Rilley](https://sierraconnect.protoexpress.com/u/Rilley)\ **Replies:** 6\ **Last updated:** [March 26, 2026, 3:38pm UTC](https://sierraconnect.protoexpress.com/t/why-consumer-power-adapters-small-appliances-often-use-single-sided-pcbs/3906 "2026-03-26T15:38:09Z")
I’ve noticed that many consumer power adapters and small appliances use single-sided FR-2 boards with through-hole components. Is it just about cost and wave soldering, or are there other manufacturing advantages to usin… --- ## [How to Design PCBs for Data Centers and AI Servers](https://sierraconnect.protoexpress.com/t/how-to-design-pcbs-for-data-centers-and-ai-servers/3942)
**Author:** [@Pooja\_Mitra](https://sierraconnect.protoexpress.com/u/Pooja_Mitra)\ **Replies:** 0\ **Last updated:** [March 26, 2026, 3:24pm UTC](https://sierraconnect.protoexpress.com/t/how-to-design-pcbs-for-data-centers-and-ai-servers/3942 "2026-03-26T15:24:16Z")
Originally published at: https://www.protoexpress.com/blog/how-to-design-pcbs-for-data-centers-and-ai-servers/ Designing PCBs for AI servers and hyperscale data center platforms requires architectures that support ex… --- ## [How do you manage design data handoff without missing critical files?](https://sierraconnect.protoexpress.com/t/how-do-you-manage-design-data-handoff-without-missing-critical-files/3938)
**Author:** [@Pooja\_Mitra](https://sierraconnect.protoexpress.com/u/Pooja_Mitra)\ **Replies:** 3\ **Last updated:** [March 25, 2026, 2:15pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-manage-design-data-handoff-without-missing-critical-files/3938 "2026-03-25T14:15:14Z")
We often see designers facing problems when handing off files to fabrication, either missing one critical file, incomplete documentation, sending outdated versions, or spending hours trying to compile Gerbers + ODB++ + s… --- ## [While requesting an assembly project I am stuck](https://sierraconnect.protoexpress.com/t/while-requesting-an-assembly-project-i-am-stuck/3932)
**Author:** [@alan1](https://sierraconnect.protoexpress.com/u/alan1)\ **Replies:** 1\ **Last updated:** [March 24, 2026, 4:04pm UTC](https://sierraconnect.protoexpress.com/t/while-requesting-an-assembly-project-i-am-stuck/3932 "2026-03-24T16:04:46Z")
I am not able to get any traction with support team, while placing our order? The support line is not picked up and messages for days are not answered? What’s the best way to get a project to move forward? --- ## [Impedance control for low-speed analog traces](https://sierraconnect.protoexpress.com/t/impedance-control-for-low-speed-analog-traces/3883)
**Author:** [@anderson](https://sierraconnect.protoexpress.com/u/anderson)\ **Replies:** 6\ **Last updated:** [March 19, 2026, 4:47pm UTC](https://sierraconnect.protoexpress.com/t/impedance-control-for-low-speed-analog-traces/3883 "2026-03-19T16:47:49Z")
For a low-speed analog signal driven by an op-amp buffer, a layout designer asked whether an analog trace should be controlled to 50 Ω. I understand 50 Ω is common for digital or RF signals, but this is a low-speed analo… --- ## [IPC-6012 or IPC-A-600: Which Standard Should You Use?](https://sierraconnect.protoexpress.com/t/ipc-6012-or-ipc-a-600-which-standard-should-you-use/3924)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 1\ **Last updated:** [March 18, 2026, 9:25pm UTC](https://sierraconnect.protoexpress.com/t/ipc-6012-or-ipc-a-600-which-standard-should-you-use/3924 "2026-03-18T21:25:30Z")
Originally published at: IPC-6012 or IPC-A-600 | Sierra Circuits The association connecting electronics industries – commonly known as IPC – is an international trade association serving the printed circuit board and… --- ## [How do you design reliable microvias?](https://sierraconnect.protoexpress.com/t/how-do-you-design-reliable-microvias/3922)
**Author:** [@Sushmitha](https://sierraconnect.protoexpress.com/u/Sushmitha)\ **Replies:** 2\ **Last updated:** [March 18, 2026, 12:42pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-design-reliable-microvias/3922 "2026-03-18T12:42:29Z")
Microvia reliability questions come up regularly during HDI layout and DFM reviews, so I wanted to start a thread on how designers approach microvia design to avoid failures during fabrication and assembly. These tiny v… --- ## [Webinar: What Your CM Wishes You Knew About Design for Assembly](https://sierraconnect.protoexpress.com/t/webinar-what-your-cm-wishes-you-knew-about-design-for-assembly/3886)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 1\ **Last updated:** [March 17, 2026, 3:54pm UTC](https://sierraconnect.protoexpress.com/t/webinar-what-your-cm-wishes-you-knew-about-design-for-assembly/3886 "2026-03-17T15:54:36Z")
Thanks for your interest in our webinar that will cover PCB design for assembly mistakes. Missed the webinar? Click the link below to watch the recording and get the slides. --- ## [Why Do PCBs Cost Less in China Than in the USA?](https://sierraconnect.protoexpress.com/t/why-do-pcbs-cost-less-in-china-than-in-the-usa/3920)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [March 17, 2026, 3:26pm UTC](https://sierraconnect.protoexpress.com/t/why-do-pcbs-cost-less-in-china-than-in-the-usa/3920 "2026-03-17T15:26:38Z")
Originally published at: https://www.protoexpress.com/blog/why-do-pcbs-cost-less-in-china-than-in-the-usa/ PCB manufacturing costs are typically lower in China than in the USA due to reduced labor expenses and large-… --- ## [Webinar: Stop Making These Medtech PCB Design Mistakes](https://sierraconnect.protoexpress.com/t/webinar-stop-making-these-medtech-pcb-design-mistakes/3916)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [March 13, 2026, 5:05pm UTC](https://sierraconnect.protoexpress.com/t/webinar-stop-making-these-medtech-pcb-design-mistakes/3916 "2026-03-13T17:05:20Z")
Thanks for your interest in our webinar. You will learn the recurring errors observed in medical boards and how to fix them. Missed the webinar? Click the link below to watch the recording and get the slides. --- ## [DDR4 layer assignment](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804)
**Author:** [@bruce\_northrop](https://sierraconnect.protoexpress.com/u/bruce_northrop)\ **Replies:** 18\ **Last updated:** [March 13, 2026, 12:50pm UTC](https://sierraconnect.protoexpress.com/t/ddr4-layer-assignment/3804 "2026-03-13T12:50:03Z")
Hello - Looking for some guidance on layer assignment for data lines on a DDR4 chip set. I’ve been all over the internet and found too much info. Can anyone provide something concise. I’ve also rerouted this a couple tim… --- ## [How do you avoid assembly errors in your layout?](https://sierraconnect.protoexpress.com/t/how-do-you-avoid-assembly-errors-in-your-layout/3907)
**Author:** [@PoulomiG](https://sierraconnect.protoexpress.com/u/PoulomiG)\ **Replies:** 2\ **Last updated:** [March 11, 2026, 12:43pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-avoid-assembly-errors-in-your-layout/3907 "2026-03-11T12:43:27Z")
We often encounter assembly-related issues during PCBA reviews, especially on dense boards, so I wanted to start a thread to discuss strategies to prevent them during the layout phase. Common causes include incomplete d… --- ## [PCB Failures. Cracked Vias and Layer Separation](https://sierraconnect.protoexpress.com/t/pcb-failures-cracked-vias-and-layer-separation/3901)
**Author:** [@ian.draney](https://sierraconnect.protoexpress.com/u/ian.draney)\ **Replies:** 4\ **Last updated:** [March 10, 2026, 10:35pm UTC](https://sierraconnect.protoexpress.com/t/pcb-failures-cracked-vias-and-layer-separation/3901 "2026-03-10T22:35:25Z")
Hello Everyone, My company has had trouble with a series of PCB failures. These failures include cracked vias and laminate separation. The via failures apply to both microvias and standard via barrels, both through-ho… --- ## [6 Decap Placement Rules for PCB Designer](https://sierraconnect.protoexpress.com/t/6-decap-placement-rules-for-pcb-designer/3904)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [March 10, 2026, 12:24pm UTC](https://sierraconnect.protoexpress.com/t/6-decap-placement-rules-for-pcb-designer/3904 "2026-03-10T12:24:48Z")
Power integrity is a critical aspect of modern PCB design. As digital devices switch faster and consume higher transient currents, maintaining a stable power supply becomes challenging. Even small voltage fluctuations… --- ## [Making Sense of Wave Soldering](https://sierraconnect.protoexpress.com/t/making-sense-of-wave-soldering/3900)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [March 6, 2026, 2:32pm UTC](https://sierraconnect.protoexpress.com/t/making-sense-of-wave-soldering/3900 "2026-03-06T14:32:54Z")
Originally published at: https://www.protoexpress.com/blog/making-sense-wave-soldering/ Depending on component technology, many options exist for automated mass soldering today. But wave soldering was the first – and… --- ## [PCB Glossary: Via-in-pad](https://sierraconnect.protoexpress.com/t/pcb-glossary-via-in-pad/3899)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [March 5, 2026, 11:32am UTC](https://sierraconnect.protoexpress.com/t/pcb-glossary-via-in-pad/3899 "2026-03-05T11:32:11Z")
Via-in-pad (VIP) is a routing technique where a hole is placed directly on the surface-mount component pad. VIP creates a vertical connection to the inner layers of a PCB. It saves routing space and supports fine-pitch … --- ## [How to Use Via-in-Pad for PCB Design and Manufacturing](https://sierraconnect.protoexpress.com/t/how-to-use-via-in-pad-for-pcb-design-and-manufacturing/3892)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [March 4, 2026, 12:09pm UTC](https://sierraconnect.protoexpress.com/t/how-to-use-via-in-pad-for-pcb-design-and-manufacturing/3892 "2026-03-04T12:09:36Z")
Originally published at: Via-in-Pad in PCB Design Manufacturing | Sierra Circuits Multi-layered printed circuit board design requires a means to establish connections between various layers. This is done using vias r… --- ## [How do you avoid common DFM issues before sending files to fab?](https://sierraconnect.protoexpress.com/t/how-do-you-avoid-common-dfm-issues-before-sending-files-to-fab/3888)
**Author:** [@milan](https://sierraconnect.protoexpress.com/u/milan)\ **Replies:** 2\ **Last updated:** [March 4, 2026, 9:07am UTC](https://sierraconnect.protoexpress.com/t/how-do-you-avoid-common-dfm-issues-before-sending-files-to-fab/3888 "2026-03-04T09:07:04Z")
One of the most frequent causes of board delays isn’t routing complexity. It’s preventable DFM issues discovered after files reach fabrication. DFM issues often arise from overlooked details in layout, stack-up, cleara… --- ## [How do you manage thermal issues in your PCB designs?](https://sierraconnect.protoexpress.com/t/how-do-you-manage-thermal-issues-in-your-pcb-designs/3882)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 2\ **Last updated:** [February 25, 2026, 12:20pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-manage-thermal-issues-in-your-pcb-designs/3882 "2026-02-25T12:20:23Z")
One of the most common queries we receive from designers is: how do I manage thermal issues in my PCB design? High temperatures on a PCB can degrade performance, reduce reliability, and cause failures over time. Thermal… --- ## [PCB Procurement Checklist for Hardware Engineers](https://sierraconnect.protoexpress.com/t/pcb-procurement-checklist-for-hardware-engineers/3878)
**Author:** [@Pooja\_Mitra](https://sierraconnect.protoexpress.com/u/Pooja_Mitra)\ **Replies:** 0\ **Last updated:** [February 24, 2026, 3:38pm UTC](https://sierraconnect.protoexpress.com/t/pcb-procurement-checklist-for-hardware-engineers/3878 "2026-02-24T15:38:19Z")
Originally published at: https://www.protoexpress.com/blog/pcb-procurement-checklist-for-hardward-engineers/ When procuring PCBs, engineering and sourcing teams should follow a structured checklist that validates BOM… --- ## [When do you choose an HDI PCB stack-up over a standard one?](https://sierraconnect.protoexpress.com/t/when-do-you-choose-an-hdi-pcb-stack-up-over-a-standard-one/3872)
**Author:** [@Pooja\_Mitra](https://sierraconnect.protoexpress.com/u/Pooja_Mitra)\ **Replies:** 2\ **Last updated:** [February 18, 2026, 1:59pm UTC](https://sierraconnect.protoexpress.com/t/when-do-you-choose-an-hdi-pcb-stack-up-over-a-standard-one/3872 "2026-02-18T13:59:06Z")
One of the most common queries we receive from designers is: how do I know if my design requires HDI or standard build-up? This usually comes up when routing starts getting tight or when a fine-pitch BGA enters the … --- ## [How manufacturers define minimum annular ring size for vias](https://sierraconnect.protoexpress.com/t/how-manufacturers-define-minimum-annular-ring-size-for-vias/3851)
**Author:** [@anderson](https://sierraconnect.protoexpress.com/u/anderson)\ **Replies:** 7\ **Last updated:** [February 13, 2026, 2:16pm UTC](https://sierraconnect.protoexpress.com/t/how-manufacturers-define-minimum-annular-ring-size-for-vias/3851 "2026-02-13T14:16:24Z")
I’ve noticed that various manufacturers recommend specific annular ring requirements for laser-drilled vias, mechanically-drilled vias, and component holes. My question is: When these minimum annular ring dimensions are… --- ## [How and when do you decide to use via filling in your PCB designs?](https://sierraconnect.protoexpress.com/t/how-and-when-do-you-decide-to-use-via-filling-in-your-pcb-designs/3860)
**Author:** [@Sushmitha](https://sierraconnect.protoexpress.com/u/Sushmitha)\ **Replies:** 2\ **Last updated:** [February 11, 2026, 11:19am UTC](https://sierraconnect.protoexpress.com/t/how-and-when-do-you-decide-to-use-via-filling-in-your-pcb-designs/3860 "2026-02-11T11:19:12Z")
We see a lot of questions around via filling strategies during layout and fabrication reviews, especially on HDI boards, BGAs, and designs targeting high-reliability assembly. I thought it would be useful to start a conv… --- ## [Common Soldering Defects in PCBs and How to Avoid Them](https://sierraconnect.protoexpress.com/t/common-soldering-defects-in-pcbs-and-how-to-avoid-them/3856)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [February 10, 2026, 1:46pm UTC](https://sierraconnect.protoexpress.com/t/common-soldering-defects-in-pcbs-and-how-to-avoid-them/3856 "2026-02-10T13:46:52Z")
Soldering defects are one of the most common causes of PCB assembly failures. Many issues are often attributed to process parameters such as stencil design and reflow profiling. Pad geometry, copper distribution, sold… --- ## [PCB Glossary: IPC Class 3](https://sierraconnect.protoexpress.com/t/pcb-glossary-ipc-class-3/3850)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [February 5, 2026, 12:40pm UTC](https://sierraconnect.protoexpress.com/t/pcb-glossary-ipc-class-3/3850 "2026-02-05T12:40:25Z")
IPC class 3 is the highest reliability performance category for rigid PCBs. It applies to mission-critical products where continuous operation is required and failure is unacceptable, such as life-support systems, flight… --- ## [How do you decide the trace width for your PCB designs?](https://sierraconnect.protoexpress.com/t/how-do-you-decide-the-trace-width-for-your-pcb-designs/3848)
**Author:** [@PoulomiG](https://sierraconnect.protoexpress.com/u/PoulomiG)\ **Replies:** 2\ **Last updated:** [February 4, 2026, 11:27am UTC](https://sierraconnect.protoexpress.com/t/how-do-you-decide-the-trace-width-for-your-pcb-designs/3848 "2026-02-04T11:27:31Z")
We often see questions about trace width selection during layout reviews, so I wanted to start a conversation here on how designers determine trace width in different scenarios. Trace width determines both current-carry… --- ## [How to bring onboard LED indicators to an enclosure exterior](https://sierraconnect.protoexpress.com/t/how-to-bring-onboard-led-indicators-to-an-enclosure-exterior/3808)
**Author:** [@anderson](https://sierraconnect.protoexpress.com/u/anderson)\ **Replies:** 5\ **Last updated:** [February 3, 2026, 5:05pm UTC](https://sierraconnect.protoexpress.com/t/how-to-bring-onboard-led-indicators-to-an-enclosure-exterior/3808 "2026-02-03T17:05:44Z")
I have a PCB mounted inside an enclosure with onboard LEDs for status indication. The LEDs aren’t visible from outside. What are the most reliable techniques to bring the LED outside of a sealed enclosure --- ## [Webinar: When PCB Design Speed Catches Up to Manufacturing](https://sierraconnect.protoexpress.com/t/webinar-when-pcb-design-speed-catches-up-to-manufacturing/3844)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [February 2, 2026, 10:50pm UTC](https://sierraconnect.protoexpress.com/t/webinar-when-pcb-design-speed-catches-up-to-manufacturing/3844 "2026-02-02T22:50:00Z")
Thanks for your interest in our webinar with Quilter on when PCB design speed catches up to manufacturing. It will be hosted on Zoom. Click the link below to register. Already registered? I will send you a confirmation… --- ## [How to quantify copper balance between PCB Layers](https://sierraconnect.protoexpress.com/t/how-to-quantify-copper-balance-between-pcb-layers/3815)
**Author:** [@mark](https://sierraconnect.protoexpress.com/u/mark)\ **Replies:** 4\ **Last updated:** [January 30, 2026, 3:16pm UTC](https://sierraconnect.protoexpress.com/t/how-to-quantify-copper-balance-between-pcb-layers/3815 "2026-01-30T15:16:16Z")
It’s common practice to balance copper between the top and bottom layers of a PCB to reduce warpage and fabrication issues. Is there a practical way to quantify copper balance (for example, percentage coverage per layer… --- ## [Ball Grid Array (BGA): Features, Soldering Technique, and X-Ray Inspection](https://sierraconnect.protoexpress.com/t/ball-grid-array-bga-features-soldering-technique-and-x-ray-inspection/3837)
**Author:** [@rahuls](https://sierraconnect.protoexpress.com/u/rahuls)\ **Replies:** 0\ **Last updated:** [January 30, 2026, 12:44pm UTC](https://sierraconnect.protoexpress.com/t/ball-grid-array-bga-features-soldering-technique-and-x-ray-inspection/3837 "2026-01-30T12:44:57Z")
Originally published at: https://www.protoexpress.com/blog/bga-features-soldering-x-ray-inspection/ Electronic devices are shrinking in size and increasing in complexity due to improvements in VLSI technology. The ne… [Previous page](https://sierraconnect.protoexpress.com/latest.md?page=5) [Next page](https://sierraconnect.protoexpress.com/latest.md?page=7)