# Latest **URL:** https://sierraconnect.protoexpress.com/latest.md?page=5 [Latest](https://sierraconnect.protoexpress.com/latest.md) · [Categories](https://sierraconnect.protoexpress.com/categories.md) · [Tags](https://sierraconnect.protoexpress.com/tags.md) **Page:** 6 --- ## [Top 10 PCB Material OEMs and Popular Laminate Families](https://sierraconnect.protoexpress.com/t/top-10-pcb-material-oems-and-popular-laminate-families/4067)
**Author:** [@Pooja\_Mitra](https://sierraconnect.protoexpress.com/u/Pooja_Mitra)\ **Replies:** 0\ **Last updated:** [May 14, 2026, 4:06pm UTC](https://sierraconnect.protoexpress.com/t/top-10-pcb-material-oems-and-popular-laminate-families/4067 "2026-05-14T16:06:01Z")
Originally published at: Top PCB Material OEMs and Laminate Families | Sierra Circuits PCB material OEMs such as Isola, Rogers, and DuPont develop laminates optimized for specific electrical and mechanical requiremen… --- ## [Webinar: Material Selection for High-Reliability Aerospace PCBs](https://sierraconnect.protoexpress.com/t/webinar-material-selection-for-high-reliability-aerospace-pcbs/4011)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 1\ **Last updated:** [May 13, 2026, 4:40pm UTC](https://sierraconnect.protoexpress.com/t/webinar-material-selection-for-high-reliability-aerospace-pcbs/4011 "2026-05-13T16:40:42Z")
Thank you for your interest in our webinar on material selection for aerospace. Missed the webinar? Click the link below to access the recording and slides. --- ## [How do you decide when a PCB trace needs termination?](https://sierraconnect.protoexpress.com/t/how-do-you-decide-when-a-pcb-trace-needs-termination/4064)
**Author:** [@milan](https://sierraconnect.protoexpress.com/u/milan)\ **Replies:** 2\ **Last updated:** [May 13, 2026, 2:22pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-decide-when-a-pcb-trace-needs-termination/4064 "2026-05-13T14:22:27Z")
We often see high-speed designs fail timing validation or exhibit intermittent data errors, not because the logic was wrong, but because trace reflections, ringing, or overshoot corrupted signal edges. In many cases, the… --- ## [Include Serial Number on Board](https://sierraconnect.protoexpress.com/t/include-serial-number-on-board/4045)
**Author:** [@allen.morrison](https://sierraconnect.protoexpress.com/u/allen.morrison)\ **Replies:** 6\ **Last updated:** [May 12, 2026, 7:45pm UTC](https://sierraconnect.protoexpress.com/t/include-serial-number-on-board/4045 "2026-05-12T19:45:32Z")
Howdy, How would I go about adding a unique serial number to each board in an order that Sierra Circuits fabricates? For example, on the silkscreen, I have the part number and revision and a place for the serial number… --- ## [Recommendations for UHV-Compatible Coax-to-PCB Connectors](https://sierraconnect.protoexpress.com/t/recommendations-for-uhv-compatible-coax-to-pcb-connectors/4060)
**Author:** [@ashen](https://sierraconnect.protoexpress.com/u/ashen)\ **Replies:** 0\ **Last updated:** [May 12, 2026, 4:15pm UTC](https://sierraconnect.protoexpress.com/t/recommendations-for-uhv-compatible-coax-to-pcb-connectors/4060 "2026-05-12T16:15:45Z")
I was reading Milan Yogendrappa’s article on mitigating outgassing effects in PCBs. I was also curious, I’m currently looking for coax-to-PCB connectors for use in a ultra high vacuum setting, does anyone have experience… --- ## [Allowable flex limits for rigid FR-4](https://sierraconnect.protoexpress.com/t/allowable-flex-limits-for-rigid-fr-4/4013)
**Author:** [@anderson](https://sierraconnect.protoexpress.com/u/anderson)\ **Replies:** 7\ **Last updated:** [May 12, 2026, 3:34pm UTC](https://sierraconnect.protoexpress.com/t/allowable-flex-limits-for-rigid-fr-4/4013 "2026-05-12T15:34:29Z")
How much flex can a standard rigid FR-4 PCB tolerate before long-term damage occurs? I understand it depends on factors such as board thickness, layer count, and board size, but is there a thumb rule for estimating a saf… --- ## [HDI vs. Standard PCB](https://sierraconnect.protoexpress.com/t/hdi-vs-standard-pcb/4056)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [May 12, 2026, 11:58am UTC](https://sierraconnect.protoexpress.com/t/hdi-vs-standard-pcb/4056 "2026-05-12T11:58:38Z")
Standard and HDI PCBs differ primarily in routing capability, via technology, fabrication complexity, and miniaturization support. Conventional multilayer boards are suitable for moderate-density layouts and standard … --- ## [Protecting exposed PCB features in conformally coated designs](https://sierraconnect.protoexpress.com/t/protecting-exposed-pcb-features-in-conformally-coated-designs/4040)
**Author:** [@anderson](https://sierraconnect.protoexpress.com/u/anderson)\ **Replies:** 6\ **Last updated:** [May 11, 2026, 2:33pm UTC](https://sierraconnect.protoexpress.com/t/protecting-exposed-pcb-features-in-conformally-coated-designs/4040 "2026-05-11T14:33:58Z")
When designing a PCB for humid environments with possible condensation, conformal coating is often used for protection. However, some areas (like connectors and pogo-pin contacts) must be masked and left uncoated. How sh… --- ## [What to know if you’re getting started in RF](https://sierraconnect.protoexpress.com/t/what-to-know-if-you-re-getting-started-in-rf/3492)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 1\ **Last updated:** [May 7, 2026, 2:31pm UTC](https://sierraconnect.protoexpress.com/t/what-to-know-if-you-re-getting-started-in-rf/3492 "2026-05-07T14:31:26Z")
When it comes to RF engineering, some building blocks are absolutely essential. In the latest Trace Talks, Neil Jarvis highlighted one of the most important: amplifiers. What makes them cornerstone compone… --- ## [PCB Glossary: Coverlay](https://sierraconnect.protoexpress.com/t/pcb-glossary-coverlay/4047)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [May 7, 2026, 10:55am UTC](https://sierraconnect.protoexpress.com/t/pcb-glossary-coverlay/4047 "2026-05-07T10:55:50Z")
A coverlay is a flexible insulating film used in flex PCBs to protect exposed copper traces from mechanical damage and contamination. It also provides electrical insulation between conductive features. The material is de… --- ## [How do you maintain signal integrity in IPC class 3 PCB designs?](https://sierraconnect.protoexpress.com/t/how-do-you-maintain-signal-integrity-in-ipc-class-3-pcb-designs/4044)
**Author:** [@Pooja\_Mitra](https://sierraconnect.protoexpress.com/u/Pooja_Mitra)\ **Replies:** 2\ **Last updated:** [May 6, 2026, 1:42pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-maintain-signal-integrity-in-ipc-class-3-pcb-designs/4044 "2026-05-06T13:42:03Z")
We often see IPC class 3 PCBs used in aerospace, medical, and defense applications experience unexpected system failures during validation, not because the design was functionally wrong, but because signal integrity (SI)… --- ## [What's New in IPC-J-STD-001J Revision?](https://sierraconnect.protoexpress.com/t/whats-new-in-ipc-j-std-001j-revision/4027)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [April 29, 2026, 3:25pm UTC](https://sierraconnect.protoexpress.com/t/whats-new-in-ipc-j-std-001j-revision/4027 "2026-04-29T15:25:33Z")
Originally published at: https://www.protoexpress.com/blog/ipc-j-std-001j-revision/ The IPC-J-STD-001J revision, released in March 2024, groups electrical clearance rules into a dedicated section, improves inspection… --- ## [How do you validate high-speed PCB performance after layout?](https://sierraconnect.protoexpress.com/t/how-do-you-validate-high-speed-pcb-performance-after-layout/4025)
**Author:** [@PoulomiG](https://sierraconnect.protoexpress.com/u/PoulomiG)\ **Replies:** 2\ **Last updated:** [April 29, 2026, 3:22pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-validate-high-speed-pcb-performance-after-layout/4025 "2026-04-29T15:22:12Z")
We often see high-speed boards that look correct in layout reviews but still fail due to unexpected signal loss, reflections, or timing issues. This usually starts showing up in designs using PCIe, USB 3.x, HDMI, Ethern… --- ## [Ask Me Anything with Ignacio de Mendizábal](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-ignacio-de-mendizabal/2668)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 17\ **Last updated:** [April 28, 2026, 10:01am UTC](https://sierraconnect.protoexpress.com/t/ask-me-anything-with-ignacio-de-mendizabal/2668 "2026-04-28T10:01:47Z")
Join our Ask Me Anything with Ignacio de Mendizábal where you can ask us questions on: • Effective EMC design strategies • Troubleshooting and debugging techniques • Overcoming challenges in high-speed and RF designs … --- ## [7 PCB Layout Design Tips for Power Electronics](https://sierraconnect.protoexpress.com/t/7-pcb-layout-design-tips-for-power-electronics/2853)
**Author:** [@Pooja\_Mitra](https://sierraconnect.protoexpress.com/u/Pooja_Mitra)\ **Replies:** 2\ **Last updated:** [April 27, 2026, 6:50pm UTC](https://sierraconnect.protoexpress.com/t/7-pcb-layout-design-tips-for-power-electronics/2853 "2026-04-27T18:50:50Z")
Originally published at: https://www.protoexpress.com/blog/pcb-layout-design-tips-for-power-electronics/ Designing PCBs for power electronics can be challenging due to the interconnected nature of electrical and ther… --- ## [Webinar: AI Enabling New Mindset for Electronics R&D](https://sierraconnect.protoexpress.com/t/webinar-ai-enabling-new-mindset-for-electronics-r-d/2804)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 2\ **Last updated:** [April 24, 2026, 4:26pm UTC](https://sierraconnect.protoexpress.com/t/webinar-ai-enabling-new-mindset-for-electronics-r-d/2804 "2026-04-24T16:26:53Z")
Thank you for your interest in our webinar on improving AI enabling new mindset for electronics R&D. It was presented by Sergiy Nesterenko, Founder and CEO of Quilter. Missed the webinar? Click the below link to watch t… --- ## [Seminar: PCB, Enclosure and Cabling Design to Control EMI by Rick Hartley](https://sierraconnect.protoexpress.com/t/seminar-pcb-enclosure-and-cabling-design-to-control-emi-by-rick-hartley/4015)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [April 23, 2026, 10:51pm UTC](https://sierraconnect.protoexpress.com/t/seminar-pcb-enclosure-and-cabling-design-to-control-emi-by-rick-hartley/4015 "2026-04-23T22:51:37Z")
Rick Hartley is coming back on October 28-29th with his famous class on PCB, enclosure and cabling design to control EMI. The seminar will cover: Energy movement in PC boards and how to control it Driving factors behi… --- ## [Webinar: How to Protect Your RF Layouts from Noise and Signal Losses](https://sierraconnect.protoexpress.com/t/webinar-how-to-protect-your-rf-layouts-from-noise-and-signal-losses/3954)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 2\ **Last updated:** [April 22, 2026, 3:38pm UTC](https://sierraconnect.protoexpress.com/t/webinar-how-to-protect-your-rf-layouts-from-noise-and-signal-losses/3954 "2026-04-22T15:38:35Z")
Thanks for your interest in our webinar on protecting RF layouts from noise. It will be presented on April 15th. Missed the webinar? Click the link below to access the recording and slides. --- ## [How do you design vias for reliable PCB performance?](https://sierraconnect.protoexpress.com/t/how-do-you-design-vias-for-reliable-pcb-performance/4010)
**Author:** [@Pooja\_Mitra](https://sierraconnect.protoexpress.com/u/Pooja_Mitra)\ **Replies:** 2\ **Last updated:** [April 22, 2026, 2:31pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-design-vias-for-reliable-pcb-performance/4010 "2026-04-22T14:31:24Z")
We often see via-related issues during layout and DFM reviews because vias are frequently chosen for routing convenience. A via may look like a simple plated hole, but it can directly impact: Manufacturability … --- ## [Heatsink placement strategies for power devices](https://sierraconnect.protoexpress.com/t/heatsink-placement-strategies-for-power-devices/3988)
**Author:** [@Rilley](https://sierraconnect.protoexpress.com/u/Rilley)\ **Replies:** 6\ **Last updated:** [April 21, 2026, 3:34pm UTC](https://sierraconnect.protoexpress.com/t/heatsink-placement-strategies-for-power-devices/3988 "2026-04-21T15:34:14Z")
When designing power modules with SMD components, what is the preferred approach for heat dissipation: placing a heatsink on the top (directly on the component) or on the bottom side of the PCB? Given that many SMD devic… --- ## [CAN Bus PCB Routing – Two Nodes with Unequal Distance to Single Connector](https://sierraconnect.protoexpress.com/t/can-bus-pcb-routing-two-nodes-with-unequal-distance-to-single-connector/3985)
**Author:** [@shyammarimuthu123](https://sierraconnect.protoexpress.com/u/shyammarimuthu123)\ **Replies:** 9\ **Last updated:** [April 18, 2026, 4:14am UTC](https://sierraconnect.protoexpress.com/t/can-bus-pcb-routing-two-nodes-with-unequal-distance-to-single-connector/3985 "2026-04-18T04:14:44Z")
Hi Friends, I am working on a PCB design with the following CAN architecture: Two MCUs on the same board Each MCU has its own CAN transceiver Both transceivers are connected to a common CANH and CANL connector … --- ## [Webinar: Key IPC Standards Every PCB Designer Should Know](https://sierraconnect.protoexpress.com/t/webinar-key-ipc-standards-every-pcb-designer-should-know/3933)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 1\ **Last updated:** [April 17, 2026, 11:27pm UTC](https://sierraconnect.protoexpress.com/t/webinar-key-ipc-standards-every-pcb-designer-should-know/3933 "2026-04-17T23:27:04Z")
Thanks for your interest in our IPC standards webinar! Missed the webinar? Click the link below to watch the recording and get the slides. --- ## [How do you decide between PTFE and non-PTFE laminates for RF designs?](https://sierraconnect.protoexpress.com/t/how-do-you-decide-between-ptfe-and-non-ptfe-laminates-for-rf-designs/3978)
**Author:** [@Zaibahmed\_Mannur](https://sierraconnect.protoexpress.com/u/Zaibahmed_Mannur)\ **Replies:** 5\ **Last updated:** [April 16, 2026, 5:05pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-decide-between-ptfe-and-non-ptfe-laminates-for-rf-designs/3978 "2026-04-16T17:05:54Z")
We often see designers struggle with material selection in RF and high-frequency PCB designs, especially when deciding between PTFE and non-PTFE laminates. I wanted to start a discussion on how engineers balance these co… --- ## [How do you manage propagation delay and timing mismatches in your PCB designs?](https://sierraconnect.protoexpress.com/t/how-do-you-manage-propagation-delay-and-timing-mismatches-in-your-pcb-designs/3994)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 2\ **Last updated:** [April 15, 2026, 2:07pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-manage-propagation-delay-and-timing-mismatches-in-your-pcb-designs/3994 "2026-04-15T14:07:47Z")
We often see timing-related issues during high-speed design review. This usually becomes critical when working with interfaces like DDR5, PCIe, HDMI, Ethernet, or USB, where timing skew and signal synchronization are tig… --- ## [AC Dimmer (FL5150) Controlled by Low-Power MCU – Grounding and Isolation](https://sierraconnect.protoexpress.com/t/ac-dimmer-fl5150-controlled-by-low-power-mcu-grounding-and-isolation/3949)
**Author:** [@rayansayedpd](https://sierraconnect.protoexpress.com/u/rayansayedpd)\ **Replies:** 1\ **Last updated:** [April 14, 2026, 2:26pm UTC](https://sierraconnect.protoexpress.com/t/ac-dimmer-fl5150-controlled-by-low-power-mcu-grounding-and-isolation/3949 "2026-04-14T14:26:22Z")
I am trying to design an AC dimmer using the FL5150, based on the datasheet reference circuit. I want to control it using a 3.3V MCU: PWM → for dimming control GPIO → for mode selection My main doubts 1. Groun… --- ## [7 Best Practices to Manage EMI in your PCBs](https://sierraconnect.protoexpress.com/t/7-best-practices-to-manage-emi-in-your-pcbs/3989)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [April 14, 2026, 1:33pm UTC](https://sierraconnect.protoexpress.com/t/7-best-practices-to-manage-emi-in-your-pcbs/3989 "2026-04-14T13:33:34Z")
Electromagnetic interference (EMI) is one of the most common causes of product failure during compliance testing. It often originates from design decisions made early in the PCB layout stage, such as stack-up, routing… --- ## [Current sharing across layers in PCB design](https://sierraconnect.protoexpress.com/t/current-sharing-across-layers-in-pcb-design/3950)
**Author:** [@mark](https://sierraconnect.protoexpress.com/u/mark)\ **Replies:** 8\ **Last updated:** [April 10, 2026, 7:15pm UTC](https://sierraconnect.protoexpress.com/t/current-sharing-across-layers-in-pcb-design/3950 "2026-04-10T19:15:06Z")
For a 14A current path, is it acceptable to route through vias, or is it better to split the current across wider traces on multiple layers (for example, 120 mil on top and 120 mil on bottom)? --- ## [Edge plating](https://sierraconnect.protoexpress.com/t/edge-plating/3966)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [April 2, 2026, 8:03am UTC](https://sierraconnect.protoexpress.com/t/edge-plating/3966 "2026-04-02T08:03:59Z")
Edge plating (also known as side plating or edge metallization) is a PCB manufacturing process where a continuous conductive layer is plated along the outer perimeter of the board. This process creates electrical connect… --- ## [How do you decide the placement of decoupling capacitors in your layout?](https://sierraconnect.protoexpress.com/t/how-do-you-decide-the-placement-of-decoupling-capacitors-in-your-layout/3955)
**Author:** [@Sushmitha](https://sierraconnect.protoexpress.com/u/Sushmitha)\ **Replies:** 2\ **Last updated:** [April 1, 2026, 1:27pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-decide-the-placement-of-decoupling-capacitors-in-your-layout/3955 "2026-04-01T13:27:33Z")
We often see placement issues with decoupling capacitors during layout and DFM reviews, especially on high-speed and dense boards. I wanted to start a discussion on how designers approach decap placement to avoid power i… --- ## [Trace width for aerospace PCBs](https://sierraconnect.protoexpress.com/t/trace-width-for-aerospace-pcbs/3873)
**Author:** [@mark](https://sierraconnect.protoexpress.com/u/mark)\ **Replies:** 8\ **Last updated:** [March 27, 2026, 2:40pm UTC](https://sierraconnect.protoexpress.com/t/trace-width-for-aerospace-pcbs/3873 "2026-03-27T14:40:35Z")
How do we determine appropriate trace width and spacing values for aerospace PCBs? [Previous page](https://sierraconnect.protoexpress.com/latest.md?page=4) [Next page](https://sierraconnect.protoexpress.com/latest.md?page=6)