# Latest **URL:** https://sierraconnect.protoexpress.com/latest.md?page=3 [Latest](https://sierraconnect.protoexpress.com/latest.md) · [Categories](https://sierraconnect.protoexpress.com/categories.md) · [Tags](https://sierraconnect.protoexpress.com/tags.md) **Page:** 4 --- ## [PCB Live Chat with Greg Albers & Steve Carney](https://sierraconnect.protoexpress.com/t/pcb-live-chat-with-greg-albers-steve-carney/4014)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 10\ **Last updated:** [July 24, 2026, 10:20pm UTC](https://sierraconnect.protoexpress.com/t/pcb-live-chat-with-greg-albers-steve-carney/4014 "2026-07-24T22:20:49Z")
Thanks for your interest in our very first PCB live chat! Click the link below to register! Already registered? I’ll send you the Zoom link by email in a few minutes. In the meantime, you can start posting your questio… --- ## [Which PCB designer are you?](https://sierraconnect.protoexpress.com/t/which-pcb-designer-are-you/4299)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [July 24, 2026, 4:05pm UTC](https://sierraconnect.protoexpress.com/t/which-pcb-designer-are-you/4299 "2026-07-24T16:05:10Z")
I’ve got this idea while watching The Big Bang Theory (although I can’t explain why) and created this fun quiz. Personally, I seem to be the PCB survivor… :grinning\_cat\_with\_smiling\_eyes: --- ## [SELV vs FELV Isolation Requirements](https://sierraconnect.protoexpress.com/t/selv-vs-felv-isolation-requirements/4276)
**Author:** [@Olivia](https://sierraconnect.protoexpress.com/u/Olivia)\ **Replies:** 3\ **Last updated:** [July 24, 2026, 2:19pm UTC](https://sierraconnect.protoexpress.com/t/selv-vs-felv-isolation-requirements/4276 "2026-07-24T14:19:41Z")
In a 230 V AC system with an RS-485 Modbus interface, what happens if the PCB cannot maintain the creepage and clearance distances required for SELV isolation? Specifically: Does that mean the entire RS-485 network mus… --- ## [Webinar: How to Nail Your HDI PCB Routing](https://sierraconnect.protoexpress.com/t/webinar-how-to-nail-your-hdi-pcb-routing/4196)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 1\ **Last updated:** [July 23, 2026, 5:22pm UTC](https://sierraconnect.protoexpress.com/t/webinar-how-to-nail-your-hdi-pcb-routing/4196 "2026-07-23T17:22:01Z")
Thanks for your interest in our HDI PCB routing webinar. Missed the webinar? Click the link below to watch the recording and get the slides. Post your questions below! --- ## [The fabrication notes most often missing from customer files](https://sierraconnect.protoexpress.com/t/the-fabrication-notes-most-often-missing-from-customer-files/4292)
**Author:** [@steve.carney](https://sierraconnect.protoexpress.com/u/steve.carney)\ **Replies:** 1\ **Last updated:** [July 23, 2026, 4:10pm UTC](https://sierraconnect.protoexpress.com/t/the-fabrication-notes-most-often-missing-from-customer-files/4292 "2026-07-23T16:10:46Z")
Here’s some of the things we often see missing or unclear at Sierra when customers send us fab notes: Controlled impedance requirements Board manufacturing specifications Which side is the primary side Material require… --- ## [Designing PCBs for space: What should you know about IPC Class 3?](https://sierraconnect.protoexpress.com/t/designing-pcbs-for-space-what-should-you-know-about-ipc-class-3/4289)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [July 22, 2026, 7:03pm UTC](https://sierraconnect.protoexpress.com/t/designing-pcbs-for-space-what-should-you-know-about-ipc-class-3/4289 "2026-07-22T19:03:59Z")
This one is for BobCAD. :grinning\_cat: When your board is going into space, reliability takes on a whole different meaning. A failure isn’t just an inconvenience, and repair or replacement may not even be an option. Duh… --- ## [How to Design High-Power PCBs for Better Fabrication and Assembly](https://sierraconnect.protoexpress.com/t/how-to-design-high-power-pcbs-for-better-fabrication-and-assembly/4284)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [July 22, 2026, 4:40pm UTC](https://sierraconnect.protoexpress.com/t/how-to-design-high-power-pcbs-for-better-fabrication-and-assembly/4284 "2026-07-22T16:40:29Z")
Originally published at: https://www.protoexpress.com/blog/how-to-design-high-power-pcbs-for-better-fabrication-and-assembly/ Designing high-power PCBs with fabrication and assembly in mind will make your manufacture… --- ## [How do you keep power supply noise away from sensitive circuits?](https://sierraconnect.protoexpress.com/t/how-do-you-keep-power-supply-noise-away-from-sensitive-circuits/4282)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 2\ **Last updated:** [July 22, 2026, 2:46pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-keep-power-supply-noise-away-from-sensitive-circuits/4282 "2026-07-22T14:46:45Z")
Power supply noise is a common source of problems in mixed-signal PCB designs. Even when the schematic is correct, poor power distribution and layout can introduce switching noise into analog, RF, or sensor circuits, lea… --- ## [What part of stack-up planning takes you the longest?](https://sierraconnect.protoexpress.com/t/what-part-of-stack-up-planning-takes-you-the-longest/4280)
**Author:** [@atar.mittal](https://sierraconnect.protoexpress.com/u/atar.mittal)\ **Replies:** 3\ **Last updated:** [July 21, 2026, 10:45pm UTC](https://sierraconnect.protoexpress.com/t/what-part-of-stack-up-planning-takes-you-the-longest/4280 "2026-07-21T22:45:27Z")
Sierra’s take: From the manufacturing side, we often see the most back-and-forth happen when the stack-up is developed too late in the design process. Material availability, finished thickness, impedance requirements, co… --- ## [What would make you participate more often?](https://sierraconnect.protoexpress.com/t/what-would-make-you-participate-more-often/4275)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 4\ **Last updated:** [July 21, 2026, 4:41pm UTC](https://sierraconnect.protoexpress.com/t/what-would-make-you-participate-more-often/4275 "2026-07-21T16:41:12Z")
Hey y’all, it’s your SierraConnect admin here. I was wondering if you could tell me what kind of topics you’d like to discuss here. Clearly, we know you won’t post here to ask what controlled impedance is when ChatGPT c… --- ## [Lecture Series: EMC 101/202 by Karen Burnham](https://sierraconnect.protoexpress.com/t/lecture-series-emc-101-202-by-karen-burnham/4278)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [July 20, 2026, 5:31pm UTC](https://sierraconnect.protoexpress.com/t/lecture-series-emc-101-202-by-karen-burnham/4278 "2026-07-20T17:31:48Z")
This lecture series by @karen.burnham is meant to be an accessible and enjoyable overview of key aspects that will make EMC issues more tractable. It includes several hands-on demonstrations, especially of unanticipated … --- ## [Seminar: Practical Design for EMC by Karen Burnham](https://sierraconnect.protoexpress.com/t/seminar-practical-design-for-emc-by-karen-burnham/4277)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [July 20, 2026, 5:29pm UTC](https://sierraconnect.protoexpress.com/t/seminar-practical-design-for-emc-by-karen-burnham/4277 "2026-07-20T17:29:13Z")
@karen.burnham is coming back on August 27th with her famous class on practical design for EMC. The seminar will cover: Choosing the right grounding and filtering scheme during circuit design The importance of solid g… --- ## [Webinar: Stack-Up Design and Part Placement for High-Power PCBs](https://sierraconnect.protoexpress.com/t/webinar-stack-up-design-and-part-placement-for-high-power-pcbs/4163)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 1\ **Last updated:** [July 20, 2026, 4:36pm UTC](https://sierraconnect.protoexpress.com/t/webinar-stack-up-design-and-part-placement-for-high-power-pcbs/4163 "2026-07-20T16:36:54Z")
Thanks for your interest in our high-power PCB webinar. Missed the webinar? Click the link below to watch the recording and get the slides. --- ## [Why do impedance mismatches cause signal reflections on PCB transmission lines?](https://sierraconnect.protoexpress.com/t/why-do-impedance-mismatches-cause-signal-reflections-on-pcb-transmission-lines/4233)
**Author:** [@anderson](https://sierraconnect.protoexpress.com/u/anderson)\ **Replies:** 5\ **Last updated:** [July 17, 2026, 3:08pm UTC](https://sierraconnect.protoexpress.com/t/why-do-impedance-mismatches-cause-signal-reflections-on-pcb-transmission-lines/4233 "2026-07-17T15:08:12Z")
I understand that an impedance mismatch causes part of a signal to be reflected back toward the source, but the physical mechanism behind it isn’t clear to me. The case I keep coming back to is series termination at the… --- ## [TEST: Which PCB Designer Are You?](https://sierraconnect.protoexpress.com/t/test-which-pcb-designer-are-you/4264)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [July 16, 2026, 7:29pm UTC](https://sierraconnect.protoexpress.com/t/test-which-pcb-designer-are-you/4264 "2026-07-16T19:29:56Z")
Originally published at: https://www.protoexpress.com/blog/test-which-pcb-designer-are-you/ How about a little PCB designer test? But the fun kind of test! Every engineering team has them. The designer who refuses to… --- ## [Starting a small contract assembly business, looking for advice from folks who've done this](https://sierraconnect.protoexpress.com/t/starting-a-small-contract-assembly-business-looking-for-advice-from-folks-whove-done-this/4258)
**Author:** [@wademallory26](https://sierraconnect.protoexpress.com/u/wademallory26)\ **Replies:** 1\ **Last updated:** [July 15, 2026, 7:03pm UTC](https://sierraconnect.protoexpress.com/t/starting-a-small-contract-assembly-business-looking-for-advice-from-folks-whove-done-this/4258 "2026-07-15T19:03:02Z")
Hey all, I’ve spent the last few years working in sales and manufacturing operations at a small meter-base surge protective device manufacturer in North Idaho, and I’m in the early stages of starting a contract electron… --- ## [How do you choose the right material for an HDI PCB?](https://sierraconnect.protoexpress.com/t/how-do-you-choose-the-right-material-for-an-hdi-pcb/4252)
**Author:** [@Sushmitha](https://sierraconnect.protoexpress.com/u/Sushmitha)\ **Replies:** 2\ **Last updated:** [July 15, 2026, 2:03pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-choose-the-right-material-for-an-hdi-pcb/4252 "2026-07-15T14:03:55Z")
Selecting the right material is one of the earliest decisions in an HDI design. It affects signal integrity, thermal reliability, laser drilling performance, manufacturability, and overall cost I wanted to start a discu… --- ## [MIL-Spec Testing Standards Every PCB Engineer Should Know](https://sierraconnect.protoexpress.com/t/mil-spec-testing-standards-every-pcb-engineer-should-know/4244)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [July 14, 2026, 12:13pm UTC](https://sierraconnect.protoexpress.com/t/mil-spec-testing-standards-every-pcb-engineer-should-know/4244 "2026-07-14T12:13:47Z")
Mil-grade PCBs must operate reliably in harsh conditions such as extreme temperatures, humidity, electromagnetic interference (EMI), and mechanical shock. To ensure consistent performance and reliability, the U.S. De… --- ## [PCB Glossary: Silkscreen](https://sierraconnect.protoexpress.com/t/pcb-glossary-silkscreen/4237)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [July 10, 2026, 8:34am UTC](https://sierraconnect.protoexpress.com/t/pcb-glossary-silkscreen/4237 "2026-07-10T08:34:46Z")
Silkscreen is the layer of printed text and symbols on a PCB. It includes reference designators, polarity markings, pin 1 indicators, test points, logos, and other assembly information. It serves as a critical visual map… --- ## [Seminar: Advanced PCB Design for Signal Integrity, Impedance, and EMI Control by Susy Webb](https://sierraconnect.protoexpress.com/t/seminar-advanced-pcb-design-for-signal-integrity-impedance-and-emi-control-by-susy-webb/4236)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [July 9, 2026, 10:58pm UTC](https://sierraconnect.protoexpress.com/t/seminar-advanced-pcb-design-for-signal-integrity-impedance-and-emi-control-by-susy-webb/4236 "2026-07-09T22:58:53Z")
Thanks for your interest in our class by Susy Webb. You can post your questions in this thread and click the link below to register. --- ## [How to Evaluate VRM Stability in PCBs](https://sierraconnect.protoexpress.com/t/how-to-evaluate-vrm-stability-in-pcbs/4234)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [July 9, 2026, 3:02pm UTC](https://sierraconnect.protoexpress.com/t/how-to-evaluate-vrm-stability-in-pcbs/4234 "2026-07-09T15:02:52Z")
Originally published at: https://www.protoexpress.com/blog/how-to-evaluate-vrm-stability-in-pcbs/ To measure the voltage regulator module (VRM) stability in PCBs, you need a combination of Bode plot analysis, step-lo… --- ## [How do you minimize signal integrity issues caused by vias in high-speed PCB designs?](https://sierraconnect.protoexpress.com/t/how-do-you-minimize-signal-integrity-issues-caused-by-vias-in-high-speed-pcb-designs/4226)
**Author:** [@Zaibahmed\_Mannur](https://sierraconnect.protoexpress.com/u/Zaibahmed_Mannur)\ **Replies:** 2\ **Last updated:** [July 8, 2026, 2:48pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-minimize-signal-integrity-issues-caused-by-vias-in-high-speed-pcb-designs/4226 "2026-07-08T14:48:19Z")
As data rates continue to increase, vias have become a critical part of the signal path rather than just interlayer connections. Every layer transition can introduce impedance discontinuities, reflections, and timing iss… --- ## [Should non-plated holes be covered by solder mask?](https://sierraconnect.protoexpress.com/t/should-non-plated-holes-be-covered-by-solder-mask/4199)
**Author:** [@Olivia](https://sierraconnect.protoexpress.com/u/Olivia)\ **Replies:** 4\ **Last updated:** [July 7, 2026, 4:12pm UTC](https://sierraconnect.protoexpress.com/t/should-non-plated-holes-be-covered-by-solder-mask/4199 "2026-07-07T16:12:50Z")
I understand the purpose of solder mask on PCB copper features, it helps prevent oxidation, reduces the risk of solder bridging, and protects areas that shouldn’t be soldered. However, I’m not sure about non-plated hole… --- ## [What is Traceability in PCB Manufacturing?](https://sierraconnect.protoexpress.com/t/what-is-traceability-in-pcb-manufacturing/4221)
**Author:** [@Pooja\_Mitra](https://sierraconnect.protoexpress.com/u/Pooja_Mitra)\ **Replies:** 0\ **Last updated:** [July 7, 2026, 3:38pm UTC](https://sierraconnect.protoexpress.com/t/what-is-traceability-in-pcb-manufacturing/4221 "2026-07-07T15:38:45Z")
Originally published at: https://www.protoexpress.com/blog/what-is-traceability-in-pcb-manufacturing/ Traceability in PCB manufacturing is the ability to track and document every stage of production. This includes ma… --- ## [Differential Pair Skew at CAN/RS-485 Termination Resistor Junction](https://sierraconnect.protoexpress.com/t/differential-pair-skew-at-can-rs-485-termination-resistor-junction/4211)
**Author:** [@shyammarimuthu123](https://sierraconnect.protoexpress.com/u/shyammarimuthu123)\ **Replies:** 1\ **Last updated:** [July 7, 2026, 9:17am UTC](https://sierraconnect.protoexpress.com/t/differential-pair-skew-at-can-rs-485-termination-resistor-junction/4211 "2026-07-07T09:17:40Z")
Hi everyone, I’m designing a PCB that includes both CAN and RS-485 interfaces. I’ve routed the differential pairs and matched the trace lengths carefully. During the differential pair skew check, I observed that the sk… --- ## [Proto Express UI](https://sierraconnect.protoexpress.com/t/proto-express-ui/4198)
**Author:** [@Ayyanar.Raja](https://sierraconnect.protoexpress.com/u/Ayyanar.Raja)\ **Replies:** 3\ **Last updated:** [July 2, 2026, 1:07am UTC](https://sierraconnect.protoexpress.com/t/proto-express-ui/4198 "2026-07-02T01:07:56Z")
Hi Team, I have small suggestion in Proto Express Website, while handling the Engineering Queries. Under the Issues Tab, the colors for all the tabs could have been same. For example, BOM Issues Details by default havi… --- ## [Webinar: Aerospace PCB Design Challenges and Techniques to Fix Them](https://sierraconnect.protoexpress.com/t/webinar-aerospace-pcb-design-challenges-and-techniques-to-fix-them/4126)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 1\ **Last updated:** [July 2, 2026, 12:59am UTC](https://sierraconnect.protoexpress.com/t/webinar-aerospace-pcb-design-challenges-and-techniques-to-fix-them/4126 "2026-07-02T00:59:28Z")
Thanks for your interest in our webinar on aerospace PCB design challenges. Missed the webinar? Click the link below to watch the recording and get the slides. --- ## [How to Design a High-Power PCB Stack-Up](https://sierraconnect.protoexpress.com/t/how-to-design-a-high-power-pcb-stack-up/4206)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [July 1, 2026, 3:30pm UTC](https://sierraconnect.protoexpress.com/t/how-to-design-a-high-power-pcb-stack-up/4206 "2026-07-01T15:30:25Z")
Originally published at: How to Design a High-Power PCB Stack-Up | Sierra Circuits When you’re working on high-power PCB stack-ups, select the right layer count, place power and ground planes close together, and opti… --- ## [How do you design an RF PCB that's easier to validate?](https://sierraconnect.protoexpress.com/t/how-do-you-design-an-rf-pcb-thats-easier-to-validate/4205)
**Author:** [@milan](https://sierraconnect.protoexpress.com/u/milan)\ **Replies:** 2\ **Last updated:** [July 1, 2026, 2:16pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-design-an-rf-pcb-thats-easier-to-validate/4205 "2026-07-01T14:16:07Z")
Getting good RF performance isn’t just about choosing the right schematic or laminate. Layout decisions made during PCB design directly affect how easy it is to validate the board once it’s fabricated. I wanted to start… --- ## [Splitting a high-current trace across top and bottom layers](https://sierraconnect.protoexpress.com/t/splitting-a-high-current-trace-across-top-and-bottom-layers/4167)
**Author:** [@Olivia](https://sierraconnect.protoexpress.com/u/Olivia)\ **Replies:** 4\ **Last updated:** [June 29, 2026, 3:03pm UTC](https://sierraconnect.protoexpress.com/t/splitting-a-high-current-trace-across-top-and-bottom-layers/4167 "2026-06-29T15:03:26Z")
For a 20 A current path on 1 oz copper, using a 20°C temperature-rise target, an online calculator suggests a trace width of about 24.8 mm. Can that width be effectively split between the top and bottom layers (for exam… [Previous page](https://sierraconnect.protoexpress.com/latest.md?page=2) [Next page](https://sierraconnect.protoexpress.com/latest.md?page=4)