# Latest **URL:** https://sierraconnect.protoexpress.com/latest.md?page=2 [Latest](https://sierraconnect.protoexpress.com/latest.md) · [Categories](https://sierraconnect.protoexpress.com/categories.md) · [Tags](https://sierraconnect.protoexpress.com/tags.md) **Page:** 3 --- ## [SPOT THE FLAW: Something was left unfinished](https://sierraconnect.protoexpress.com/t/spot-the-flaw-something-was-left-unfinished/4388)
**Author:** [@rahuls](https://sierraconnect.protoexpress.com/u/rahuls)\ **Replies:** 1\ **Last updated:** [August 21, 2026, 5:23am UTC](https://sierraconnect.protoexpress.com/t/spot-the-flaw-something-was-left-unfinished/4388 "2026-08-21T05:23:52Z")
Answer on Friday --- ## [What do you wish you had learned earlier in your PCB career?](https://sierraconnect.protoexpress.com/t/what-do-you-wish-you-had-learned-earlier-in-your-pcb-career/4391)
**Author:** [@rahuls](https://sierraconnect.protoexpress.com/u/rahuls)\ **Replies:** 0\ **Last updated:** [August 20, 2026, 2:35pm UTC](https://sierraconnect.protoexpress.com/t/what-do-you-wish-you-had-learned-earlier-in-your-pcb-career/4391 "2026-08-20T14:35:17Z")
I came into the PCB industry from the content and marketing side, and one thing I wish I had understood earlier is that you can’t really write good technical blogs just by reading glossaries and doing research. In my fi… --- ## [How do you keep power supplies clean for clocks and other sensitive circuits?](https://sierraconnect.protoexpress.com/t/how-do-you-keep-power-supplies-clean-for-clocks-and-other-sensitive-circuits/4386)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 2\ **Last updated:** [August 19, 2026, 2:25pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-keep-power-supplies-clean-for-clocks-and-other-sensitive-circuits/4386 "2026-08-19T14:25:29Z")
Clock performance can be affected by noise on its power supply, especially in designs using high-speed clocks, ADCs, or other timing-sensitive circuits. A regulator may provide the required voltage, but that doesn’t nece… --- ## [8 Factors that Lead to Signal Integrity Issues in a PCB](https://sierraconnect.protoexpress.com/t/8-factors-that-lead-to-signal-integrity-issues-in-a-pcb/4385)
**Author:** [@rahuls](https://sierraconnect.protoexpress.com/u/rahuls)\ **Replies:** 0\ **Last updated:** [August 19, 2026, 12:09pm UTC](https://sierraconnect.protoexpress.com/t/8-factors-that-lead-to-signal-integrity-issues-in-a-pcb/4385 "2026-08-19T12:09:52Z")
Originally published at: https://www.protoexpress.com/blog/signal-integrity-issues-in-pcb/ Avoiding signal integrity issues in a PCB is an extremely complex task for designers. It requires a deep understanding of sig… --- ## [Schematic vs layout: What changes when the board design begins?](https://sierraconnect.protoexpress.com/t/schematic-vs-layout-what-changes-when-the-board-design-begins/4381)
**Author:** [@rahuls](https://sierraconnect.protoexpress.com/u/rahuls)\ **Replies:** 0\ **Last updated:** [August 18, 2026, 2:02pm UTC](https://sierraconnect.protoexpress.com/t/schematic-vs-layout-what-changes-when-the-board-design-begins/4381 "2026-08-18T14:02:43Z")
One of the most common misconceptions I see is that PCB layout is simply the process of drawing copper traces after the schematic is finished. In reality, that’s where many of the most important engineering decisions beg… --- ## [Blind via design and PCB fabrication constraints](https://sierraconnect.protoexpress.com/t/blind-via-design-and-pcb-fabrication-constraints/4346)
**Author:** [@anderson](https://sierraconnect.protoexpress.com/u/anderson)\ **Replies:** 4\ **Last updated:** [August 17, 2026, 2:55pm UTC](https://sierraconnect.protoexpress.com/t/blind-via-design-and-pcb-fabrication-constraints/4346 "2026-08-17T14:55:25Z")
When designing HDI or high-density boards, blind vias help free up routing space and cut down on via transitions, but I’ve noticed some PCB manufacturers don’t list them as a standard capability, or they require extra re… --- ## [Typical Signal Integrity Issues PCB Designers Should Watch Out For](https://sierraconnect.protoexpress.com/t/typical-signal-integrity-issues-pcb-designers-should-watch-out-for/4378)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [August 17, 2026, 1:41pm UTC](https://sierraconnect.protoexpress.com/t/typical-signal-integrity-issues-pcb-designers-should-watch-out-for/4378 "2026-08-17T13:41:07Z")
As signal rise times become faster and data rates increase, PCB traces can no longer be treated as simple electrical connections. Trace impedance, return current paths, coupling between adjacent conductors, and power … --- ## [What’s the biggest lie in PCB design?](https://sierraconnect.protoexpress.com/t/what-s-the-biggest-lie-in-pcb-design/4372)
**Author:** [@rahuls](https://sierraconnect.protoexpress.com/u/rahuls)\ **Replies:** 0\ **Last updated:** [August 14, 2026, 3:52pm UTC](https://sierraconnect.protoexpress.com/t/what-s-the-biggest-lie-in-pcb-design/4372 "2026-08-14T15:52:55Z")
“This is the final revision.” --- ## [SPOT THE FLAW: Look beneath the package](https://sierraconnect.protoexpress.com/t/spot-the-flaw-look-beneath-the-package/4357)
**Author:** [@rahuls](https://sierraconnect.protoexpress.com/u/rahuls)\ **Replies:** 1\ **Last updated:** [August 14, 2026, 5:55am UTC](https://sierraconnect.protoexpress.com/t/spot-the-flaw-look-beneath-the-package/4357 "2026-08-14T05:55:04Z")
Answer on Friday --- ## [How do you ensure your PCB design is ready for RoHS-compliant manufacturing?](https://sierraconnect.protoexpress.com/t/how-do-you-ensure-your-pcb-design-is-ready-for-rohs-compliant-manufacturing/4356)
**Author:** [@Zaibahmed\_Mannur](https://sierraconnect.protoexpress.com/u/Zaibahmed_Mannur)\ **Replies:** 2\ **Last updated:** [August 12, 2026, 1:56pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-ensure-your-pcb-design-is-ready-for-rohs-compliant-manufacturing/4356 "2026-08-12T13:56:16Z")
RoHS compliance isn’t something to check only after the PCB is designed. Material selection, surface finish, component requirements, and assembly temperatures can all affect whether a board is ready for lead-free RoHS-co… --- ## [Rigid-Flex Layer Preference](https://sierraconnect.protoexpress.com/t/rigid-flex-layer-preference/4340)
**Author:** [@phil.holden](https://sierraconnect.protoexpress.com/u/phil.holden)\ **Replies:** 3\ **Last updated:** [August 12, 2026, 1:41pm UTC](https://sierraconnect.protoexpress.com/t/rigid-flex-layer-preference/4340 "2026-08-12T13:41:49Z")
For a 2-layer rigid-flex with a single-layer flex limb, do you have a fabrication preference for whether the flex copper continues from the top or bottom rigid layer, or is either acceptable? --- ## [The History of Flexible PCBs and Their Modern Application](https://sierraconnect.protoexpress.com/t/the-history-of-flexible-pcbs-and-their-modern-application/4354)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [August 12, 2026, 12:20pm UTC](https://sierraconnect.protoexpress.com/t/the-history-of-flexible-pcbs-and-their-modern-application/4354 "2026-08-12T12:20:59Z")
Originally published at: https://www.protoexpress.com/blog/the-history-of-flexible-pcbs-and-their-modern-applications/ Modern electronics manufacturers often face contradictory requirements when integrating complex c… --- ## [COURSE: EMC testing by Karen Burnham](https://sierraconnect.protoexpress.com/t/course-emc-testing-by-karen-burnham/4351)
**Author:** [@rahuls](https://sierraconnect.protoexpress.com/u/rahuls)\ **Replies:** 0\ **Last updated:** [August 11, 2026, 2:49pm UTC](https://sierraconnect.protoexpress.com/t/course-emc-testing-by-karen-burnham/4351 "2026-08-11T14:49:00Z")
We recently had the pleasure of hosting Karen Burnham for a full-day seminar on EMC testing, and we didn’t want the learning to stop there. We’ve now turned the recording into an on-demand course on Sierra Academy, so a… --- ## [How many design reviews does your board receive?](https://sierraconnect.protoexpress.com/t/how-many-design-reviews-does-your-board-receive/4345)
**Author:** [@rahuls](https://sierraconnect.protoexpress.com/u/rahuls)\ **Replies:** 0\ **Last updated:** [August 10, 2026, 2:12pm UTC](https://sierraconnect.protoexpress.com/t/how-many-design-reviews-does-your-board-receive/4345 "2026-08-10T14:12:07Z")
poll Other? Comment in the thread. --- ## [SPOT THE FLAW: This trace is carrying more than just a signal](https://sierraconnect.protoexpress.com/t/spot-the-flaw-this-trace-is-carrying-more-than-just-a-signal/4335)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 2\ **Last updated:** [August 7, 2026, 8:27pm UTC](https://sierraconnect.protoexpress.com/t/spot-the-flaw-this-trace-is-carrying-more-than-just-a-signal/4335 "2026-08-07T20:27:24Z")
Answer on Friday… --- ## [PCB designer pet peeves: What annoys you the most?](https://sierraconnect.protoexpress.com/t/pcb-designer-pet-peeves-what-annoys-you-the-most/4341)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [August 7, 2026, 3:16pm UTC](https://sierraconnect.protoexpress.com/t/pcb-designer-pet-peeves-what-annoys-you-the-most/4341 "2026-08-07T15:16:25Z")
poll PS: I told my cats to tell your cats that tomorrow is International Cat Day. Spoil them or live to regret it. --- ## [PCB Glossary: Creepage and clearance](https://sierraconnect.protoexpress.com/t/pcb-glossary-creepage-and-clearance/4338)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [August 6, 2026, 12:49pm UTC](https://sierraconnect.protoexpress.com/t/pcb-glossary-creepage-and-clearance/4338 "2026-08-06T12:49:40Z")
Creepage and clearance are the physical spacing required between conductive features to ensure electrical insulation and prevent dielectric breakdown in high-voltage PCB designs. Creepage: The shortest distance measure… --- ## [Webinar: How to Strategically Plan EMC-compliant PCB Stack-Ups](https://sierraconnect.protoexpress.com/t/webinar-how-to-strategically-plan-emc-compliant-pcb-stack-ups/4238)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 4\ **Last updated:** [August 5, 2026, 3:13pm UTC](https://sierraconnect.protoexpress.com/t/webinar-how-to-strategically-plan-emc-compliant-pcb-stack-ups/4238 "2026-08-05T15:13:31Z")
Thanks for your interest in our EMC-compliant stack-up webinar with special Q&A by Kenneth Wyatt. Missed the webinar? Click the link below to watch the recording and get the slides. Visit @ken’s Bench Top EMC website. … --- ## [What's your approach to BGA fanout before routing the rest of the board?](https://sierraconnect.protoexpress.com/t/whats-your-approach-to-bga-fanout-before-routing-the-rest-of-the-board/4336)
**Author:** [@milan](https://sierraconnect.protoexpress.com/u/milan)\ **Replies:** 2\ **Last updated:** [August 5, 2026, 2:33pm UTC](https://sierraconnect.protoexpress.com/t/whats-your-approach-to-bga-fanout-before-routing-the-rest-of-the-board/4336 "2026-08-05T14:33:39Z")
BGA escape routing is often one of the most challenging parts of PCB layout, especially for fine-pitch devices. It’s tempting to start routing interfaces immediately, but doing so too early can make it difficult to escap… --- ## [Better DFM tip: Three checks to run before submission](https://sierraconnect.protoexpress.com/t/better-dfm-tip-three-checks-to-run-before-submission/4332)
**Author:** [@atar.mittal](https://sierraconnect.protoexpress.com/u/atar.mittal)\ **Replies:** 1\ **Last updated:** [August 4, 2026, 3:13pm UTC](https://sierraconnect.protoexpress.com/t/better-dfm-tip-three-checks-to-run-before-submission/4332 "2026-08-04T15:13:11Z")
I’ve seen plenty of PC boards that were electrically sound but still ended up on hold bc of few manufacturability issues that could have been caught in 5 mins. Before you release a design these are 3 things you must alw… --- ## [POLL: At what trace/space do you involve your fabricator?](https://sierraconnect.protoexpress.com/t/poll-at-what-trace-space-do-you-involve-your-fabricator/4330)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [August 3, 2026, 10:50pm UTC](https://sierraconnect.protoexpress.com/t/poll-at-what-trace-space-do-you-involve-your-fabricator/4330 "2026-08-03T22:50:05Z")
poll --- ## [Ask Greg: What makes a layout manufacturable?](https://sierraconnect.protoexpress.com/t/ask-greg-what-makes-a-layout-manufacturable/4329)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [August 3, 2026, 4:18pm UTC](https://sierraconnect.protoexpress.com/t/ask-greg-what-makes-a-layout-manufacturable/4329 "2026-08-03T16:18:05Z")
Lucy: So I I need to ask you something. What makes a layout manufacturable? Following all the right rules. Simple answer. Now what are the right rules? That’s the complex part. Basically it’s following all the righ… --- ## [SPOT THE FLAW: Something isn't quite... positive](https://sierraconnect.protoexpress.com/t/spot-the-flaw-something-isnt-quite-positive/4317)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 2\ **Last updated:** [July 31, 2026, 7:17pm UTC](https://sierraconnect.protoexpress.com/t/spot-the-flaw-something-isnt-quite-positive/4317 "2026-07-31T19:17:22Z")
--- ## [Can return path discontinuities cause conducted emissions on a 4-Layer PCB?](https://sierraconnect.protoexpress.com/t/can-return-path-discontinuities-cause-conducted-emissions-on-a-4-layer-pcb/4304)
**Author:** [@johnkl](https://sierraconnect.protoexpress.com/u/johnkl)\ **Replies:** 4\ **Last updated:** [July 31, 2026, 11:41am UTC](https://sierraconnect.protoexpress.com/t/can-return-path-discontinuities-cause-conducted-emissions-on-a-4-layer-pcb/4304 "2026-07-31T11:41:58Z")
I’m investigating a conducted emissions issue on a 4-layer PCB and would like to sanity-check my understanding of the return-current path. Stackup: L1 (Top): Signals + stitched GND pour (0.065 mm to L2) L2: Solid GND … --- ## [Finish the sentence: “It passed DRC, but…”](https://sierraconnect.protoexpress.com/t/finish-the-sentence-it-passed-drc-but/4324)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [July 30, 2026, 4:54pm UTC](https://sierraconnect.protoexpress.com/t/finish-the-sentence-it-passed-drc-but/4324 "2026-07-30T16:54:03Z")
…the fab had other plans. --- ## [Design Considerations for LPDDR4/LPDDR5 Signal Probing](https://sierraconnect.protoexpress.com/t/design-considerations-for-lpddr4-lpddr5-signal-probing/4321)
**Author:** [@harshitshakya49](https://sierraconnect.protoexpress.com/u/harshitshakya49)\ **Replies:** 2\ **Last updated:** [July 30, 2026, 1:36pm UTC](https://sierraconnect.protoexpress.com/t/design-considerations-for-lpddr4-lpddr5-signal-probing/4321 "2026-07-30T13:36:09Z")
Hi everyone, We are designing two different boards: - Board 1: LPDDR4 - Board 2: LPDDR5 For both boards, we need to perform signal probing during hardware validation and debugging. I would like to know the recommend… --- ## [How do you decide when via stubs need to be removed?](https://sierraconnect.protoexpress.com/t/how-do-you-decide-when-via-stubs-need-to-be-removed/4316)
**Author:** [@Pooja\_Mitra](https://sierraconnect.protoexpress.com/u/Pooja_Mitra)\ **Replies:** 2\ **Last updated:** [July 29, 2026, 1:57pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-decide-when-via-stubs-need-to-be-removed/4316 "2026-07-29T13:57:51Z")
Via stubs are easy to overlook because they don’t always create problems. In many designs, they’re harmless. But as signal rise times get faster and data rates increase, the unused portion of a via can begin to affect si… --- ## [Steps to generate a stack-up with the Stackup Designer tool](https://sierraconnect.protoexpress.com/t/steps-to-generate-a-stack-up-with-the-stackup-designer-tool/4313)
**Author:** [@atar.mittal](https://sierraconnect.protoexpress.com/u/atar.mittal)\ **Replies:** 0\ **Last updated:** [July 28, 2026, 4:30pm UTC](https://sierraconnect.protoexpress.com/t/steps-to-generate-a-stack-up-with-the-stackup-designer-tool/4313 "2026-07-28T16:30:03Z")
This section shows the steps to create build-ups for low-cost, standard, high-power, high-frequency, and HDI PCBs. Step 1: Provide the following project details: Project name PCB size (length and breadth) Layer count P… --- ## [SPOT THE FLAW: Sometimes, taking too many shortcuts actually makes the journey worse](https://sierraconnect.protoexpress.com/t/spot-the-flaw-sometimes-taking-too-many-shortcuts-actually-makes-the-journey-worse/4283)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 2\ **Last updated:** [July 27, 2026, 8:09pm UTC](https://sierraconnect.protoexpress.com/t/spot-the-flaw-sometimes-taking-too-many-shortcuts-actually-makes-the-journey-worse/4283 "2026-07-27T20:09:53Z")
--- ## [POLL: How early do you think about DFA?](https://sierraconnect.protoexpress.com/t/poll-how-early-do-you-think-about-dfa/4308)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [July 27, 2026, 8:05pm UTC](https://sierraconnect.protoexpress.com/t/poll-how-early-do-you-think-about-dfa/4308 "2026-07-27T20:05:59Z")
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