# Latest **URL:** https://sierraconnect.protoexpress.com/latest.md?page=1 [Latest](https://sierraconnect.protoexpress.com/latest.md) · [Categories](https://sierraconnect.protoexpress.com/categories.md) · [Tags](https://sierraconnect.protoexpress.com/tags.md) **Page:** 2 --- ## [Sierrathon 2026](https://sierraconnect.protoexpress.com/t/sierrathon-2026/4425)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 3\ **Last updated:** [September 4, 2026, 4:33pm UTC](https://sierraconnect.protoexpress.com/t/sierrathon-2026/4425 "2026-09-04T16:33:05Z")
Put your PCB skills to the test! Sierrathon is not your average design competition, it’s a high-energy, fast-paced challenge where engineering students tackle real-world PCB design problems. Over the course of one day, t… --- ## [How do wave-solderable smd packages survive direct wave contact](https://sierraconnect.protoexpress.com/t/how-do-wave-solderable-smd-packages-survive-direct-wave-contact/4327)
**Author:** [@mark](https://sierraconnect.protoexpress.com/u/mark)\ **Replies:** 4\ **Last updated:** [September 4, 2026, 3:19pm UTC](https://sierraconnect.protoexpress.com/t/how-do-wave-solderable-smd-packages-survive-direct-wave-contact/4327 "2026-09-04T15:19:55Z")
I know wave soldering is primarily used for through-hole components, but I’ve also read that certain SMD components can be wave soldered on mixed-technology boards. What I’m trying to understand is what actually comes i… --- ## [Webinar: Practical EMI Reduction Techniques Every PCB Designer Should Know](https://sierraconnect.protoexpress.com/t/webinar-practical-emi-reduction-techniques-every-pcb-designer-should-know/4326)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 1\ **Last updated:** [September 3, 2026, 5:22pm UTC](https://sierraconnect.protoexpress.com/t/webinar-practical-emi-reduction-techniques-every-pcb-designer-should-know/4326 "2026-09-03T17:22:16Z")
Thanks for your interest in our webinar on EMI reduction with special Q&A by @karen.burnham! Missed the webinar? Click the link below to access the recording and slides. 📅 August 26, 2026 9:00 AM → August 26, 2026 10:0… --- ## [Replacing power trace with a copper pour in dense layouts](https://sierraconnect.protoexpress.com/t/replacing-power-trace-with-a-copper-pour-in-dense-layouts/4382)
**Author:** [@anderson](https://sierraconnect.protoexpress.com/u/anderson)\ **Replies:** 5\ **Last updated:** [September 3, 2026, 4:55pm UTC](https://sierraconnect.protoexpress.com/t/replacing-power-trace-with-a-copper-pour-in-dense-layouts/4382 "2026-09-03T16:55:55Z")
I need to route a power rail carrying a current of 5 A with a temp rise of 20oc and 1 oz copper. Based on standard trace width calculators, this requires roughly a 95-mil equivalent trace width. But the component density… --- ## [PCB Glossary: Thermal cycling](https://sierraconnect.protoexpress.com/t/pcb-glossary-thermal-cycling/4438)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [September 3, 2026, 11:04am UTC](https://sierraconnect.protoexpress.com/t/pcb-glossary-thermal-cycling/4438 "2026-09-03T11:04:54Z")
PCB thermal cycling is a type of circuit board test that exposes a board to repeated predetermined high and low temperatures. It evaluates how well the circuit board materials, interconnections, and components withstand … --- ## [What soldering tips do you pay the most attention to during PCB assembly?](https://sierraconnect.protoexpress.com/t/what-soldering-tips-do-you-pay-the-most-attention-to-during-pcb-assembly/4429)
**Author:** [@Sushmitha](https://sierraconnect.protoexpress.com/u/Sushmitha)\ **Replies:** 3\ **Last updated:** [September 2, 2026, 3:25pm UTC](https://sierraconnect.protoexpress.com/t/what-soldering-tips-do-you-pay-the-most-attention-to-during-pcb-assembly/4429 "2026-09-02T15:25:29Z")
Last week, we discussed how to design for reliable PCB soldering, covering pad geometry, thermal balance, component spacing, and surface finish. This post continues that discussion with a few practical soldering tips tha… --- ## [PCB material selection course](https://sierraconnect.protoexpress.com/t/pcb-material-selection-course/4427)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [September 1, 2026, 4:12pm UTC](https://sierraconnect.protoexpress.com/t/pcb-material-selection-course/4427 "2026-09-01T16:12:30Z")
PCB material selection can get complicated fast, especially when you’re trying to balance performance with cost and manufacturability. We put together a 60-minute PCB material selection course that breaks down how signa… --- ## [Floating Copper Island on Internal 3.3V Plane: Keep or Void?](https://sierraconnect.protoexpress.com/t/floating-copper-island-on-internal-3-3v-plane-keep-or-void/4408)
**Author:** [@johnkl](https://sierraconnect.protoexpress.com/u/johnkl)\ **Replies:** 4\ **Last updated:** [September 1, 2026, 1:54pm UTC](https://sierraconnect.protoexpress.com/t/floating-copper-island-on-internal-3-3v-plane-keep-or-void/4408 "2026-09-01T13:54:22Z")
4-layer board: Top / GND / 3.3V / Bottom. My internal 3.3V plane has a large region that can’t connect to the main polygon without violating clearance rules. Should I leave this as floating copper for copper balance, or… --- ## [SPOT THE FLAW: Look closely at the boundaries of the copper regions](https://sierraconnect.protoexpress.com/t/spot-the-flaw-look-closely-at-the-boundaries-of-the-copper-regions/4416)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 1\ **Last updated:** [August 28, 2026, 10:24pm UTC](https://sierraconnect.protoexpress.com/t/spot-the-flaw-look-closely-at-the-boundaries-of-the-copper-regions/4416 "2026-08-28T22:24:30Z")
Answer on Friday… --- ## [What file causes the most confusion before fabrication?](https://sierraconnect.protoexpress.com/t/what-file-causes-the-most-confusion-before-fabrication/4426)
**Author:** [@atar.mittal](https://sierraconnect.protoexpress.com/u/atar.mittal)\ **Replies:** 0\ **Last updated:** [August 28, 2026, 9:28pm UTC](https://sierraconnect.protoexpress.com/t/what-file-causes-the-most-confusion-before-fabrication/4426 "2026-08-28T21:28:08Z")
poll --- ## [What actually causes PCB warpage? And can it be fixed?](https://sierraconnect.protoexpress.com/t/what-actually-causes-pcb-warpage-and-can-it-be-fixed/4423)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [August 27, 2026, 5:08pm UTC](https://sierraconnect.protoexpress.com/t/what-actually-causes-pcb-warpage-and-can-it-be-fixed/4423 "2026-08-27T17:08:56Z")
An unbalanced stack-up is not a great start but there’s more. In this video, we’re on the manufacturing floor with Billy looking at how we check a PCB for warpage, what can cause a board to bow or twist, and what we … --- ## [Microvia Aspect Ratio: The One HDI Design Mistake That Messes Up Your PCB](https://sierraconnect.protoexpress.com/t/microvia-aspect-ratio-the-one-hdi-design-mistake-that-messes-up-your-pcb/4415)
**Author:** [@milan](https://sierraconnect.protoexpress.com/u/milan)\ **Replies:** 0\ **Last updated:** [August 26, 2026, 3:19pm UTC](https://sierraconnect.protoexpress.com/t/microvia-aspect-ratio-the-one-hdi-design-mistake-that-messes-up-your-pcb/4415 "2026-08-26T15:19:19Z")
Originally published at: Microvia Aspect Ratio: HDI Design Mistake | Sierra Circuits Designing a microvia with an excessive aspect ratio is one of the typical causes of reliability issues in HDI PCBs. It can result i… --- ## [How do you design for reliable PCB soldering?](https://sierraconnect.protoexpress.com/t/how-do-you-design-for-reliable-pcb-soldering/4412)
**Author:** [@Sushmitha](https://sierraconnect.protoexpress.com/u/Sushmitha)\ **Replies:** 2\ **Last updated:** [August 26, 2026, 1:03pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-design-for-reliable-pcb-soldering/4412 "2026-08-26T13:03:51Z")
A PCB can be electrically correct and still run into soldering problems during assembly. Pad geometry, component spacing, thermal balance, surface finish, and solder paste application all influence how reliably component… --- ## [Skills needed for a first PCB design job](https://sierraconnect.protoexpress.com/t/skills-needed-for-a-first-pcb-design-job/4409)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [August 25, 2026, 3:45pm UTC](https://sierraconnect.protoexpress.com/t/skills-needed-for-a-first-pcb-design-job/4409 "2026-08-25T15:45:20Z")
A lot of you are going back to school, maybe some of you are looking for a job, and even maybe some of you want to become PCB designers. We have a blog that explains how to become a PCB designer in 2026: Learn how to … --- ## [POLL: Which PCB career path interests you most?](https://sierraconnect.protoexpress.com/t/poll-which-pcb-career-path-interests-you-most/4404)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 1\ **Last updated:** [August 24, 2026, 3:59pm UTC](https://sierraconnect.protoexpress.com/t/poll-which-pcb-career-path-interests-you-most/4404 "2026-08-24T15:59:01Z")
poll --- ## [PCB Manufacturing Inquiry – 0.15 mm Microvias, Buried Vias and Mech through-hole Vias](https://sierraconnect.protoexpress.com/t/pcb-manufacturing-inquiry-0-15-mm-microvias-buried-vias-and-mech-through-hole-vias/4384)
**Author:** [@jjiang](https://sierraconnect.protoexpress.com/u/jjiang)\ **Replies:** 6\ **Last updated:** [August 24, 2026, 3:51pm UTC](https://sierraconnect.protoexpress.com/t/pcb-manufacturing-inquiry-0-15-mm-microvias-buried-vias-and-mech-through-hole-vias/4384 "2026-08-24T15:51:18Z")
I would like to ask about Sierra manufacturing capability for a 10-layer PCB with 0.15 mm microvias, buried vias and through-hole PTHs. I want to design a PCB that is 1.6 mm thick and has a BGA requiring fan-out. The vi… --- ## [PCB terminology matching game](https://sierraconnect.protoexpress.com/t/pcb-terminology-matching-game/4396)
**Author:** [@rahuls](https://sierraconnect.protoexpress.com/u/rahuls)\ **Replies:** 0\ **Last updated:** [August 21, 2026, 1:21pm UTC](https://sierraconnect.protoexpress.com/t/pcb-terminology-matching-game/4396 "2026-08-21T13:21:42Z")
Match each PCB term with its definition. Terms A. Annular ring B. Teardrop C. Via stub D. Solder mask dam E. Thermal relief Definitions Extra copper added where a trace meets a pad to improve reliability. Copper re… --- ## [SPOT THE FLAW: Something was left unfinished](https://sierraconnect.protoexpress.com/t/spot-the-flaw-something-was-left-unfinished/4388)
**Author:** [@rahuls](https://sierraconnect.protoexpress.com/u/rahuls)\ **Replies:** 1\ **Last updated:** [August 21, 2026, 5:23am UTC](https://sierraconnect.protoexpress.com/t/spot-the-flaw-something-was-left-unfinished/4388 "2026-08-21T05:23:52Z")
Answer on Friday --- ## [What do you wish you had learned earlier in your PCB career?](https://sierraconnect.protoexpress.com/t/what-do-you-wish-you-had-learned-earlier-in-your-pcb-career/4391)
**Author:** [@rahuls](https://sierraconnect.protoexpress.com/u/rahuls)\ **Replies:** 0\ **Last updated:** [August 20, 2026, 2:35pm UTC](https://sierraconnect.protoexpress.com/t/what-do-you-wish-you-had-learned-earlier-in-your-pcb-career/4391 "2026-08-20T14:35:17Z")
I came into the PCB industry from the content and marketing side, and one thing I wish I had understood earlier is that you can’t really write good technical blogs just by reading glossaries and doing research. In my fi… --- ## [How do you keep power supplies clean for clocks and other sensitive circuits?](https://sierraconnect.protoexpress.com/t/how-do-you-keep-power-supplies-clean-for-clocks-and-other-sensitive-circuits/4386)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 2\ **Last updated:** [August 19, 2026, 2:25pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-keep-power-supplies-clean-for-clocks-and-other-sensitive-circuits/4386 "2026-08-19T14:25:29Z")
Clock performance can be affected by noise on its power supply, especially in designs using high-speed clocks, ADCs, or other timing-sensitive circuits. A regulator may provide the required voltage, but that doesn’t nece… --- ## [8 Factors that Lead to Signal Integrity Issues in a PCB](https://sierraconnect.protoexpress.com/t/8-factors-that-lead-to-signal-integrity-issues-in-a-pcb/4385)
**Author:** [@rahuls](https://sierraconnect.protoexpress.com/u/rahuls)\ **Replies:** 0\ **Last updated:** [August 19, 2026, 12:09pm UTC](https://sierraconnect.protoexpress.com/t/8-factors-that-lead-to-signal-integrity-issues-in-a-pcb/4385 "2026-08-19T12:09:52Z")
Originally published at: https://www.protoexpress.com/blog/signal-integrity-issues-in-pcb/ Avoiding signal integrity issues in a PCB is an extremely complex task for designers. It requires a deep understanding of sig… --- ## [Schematic vs layout: What changes when the board design begins?](https://sierraconnect.protoexpress.com/t/schematic-vs-layout-what-changes-when-the-board-design-begins/4381)
**Author:** [@rahuls](https://sierraconnect.protoexpress.com/u/rahuls)\ **Replies:** 0\ **Last updated:** [August 18, 2026, 2:02pm UTC](https://sierraconnect.protoexpress.com/t/schematic-vs-layout-what-changes-when-the-board-design-begins/4381 "2026-08-18T14:02:43Z")
One of the most common misconceptions I see is that PCB layout is simply the process of drawing copper traces after the schematic is finished. In reality, that’s where many of the most important engineering decisions beg… --- ## [Blind via design and PCB fabrication constraints](https://sierraconnect.protoexpress.com/t/blind-via-design-and-pcb-fabrication-constraints/4346)
**Author:** [@anderson](https://sierraconnect.protoexpress.com/u/anderson)\ **Replies:** 4\ **Last updated:** [August 17, 2026, 2:55pm UTC](https://sierraconnect.protoexpress.com/t/blind-via-design-and-pcb-fabrication-constraints/4346 "2026-08-17T14:55:25Z")
When designing HDI or high-density boards, blind vias help free up routing space and cut down on via transitions, but I’ve noticed some PCB manufacturers don’t list them as a standard capability, or they require extra re… --- ## [Typical Signal Integrity Issues PCB Designers Should Watch Out For](https://sierraconnect.protoexpress.com/t/typical-signal-integrity-issues-pcb-designers-should-watch-out-for/4378)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [August 17, 2026, 1:41pm UTC](https://sierraconnect.protoexpress.com/t/typical-signal-integrity-issues-pcb-designers-should-watch-out-for/4378 "2026-08-17T13:41:07Z")
As signal rise times become faster and data rates increase, PCB traces can no longer be treated as simple electrical connections. Trace impedance, return current paths, coupling between adjacent conductors, and power … --- ## [What’s the biggest lie in PCB design?](https://sierraconnect.protoexpress.com/t/what-s-the-biggest-lie-in-pcb-design/4372)
**Author:** [@rahuls](https://sierraconnect.protoexpress.com/u/rahuls)\ **Replies:** 0\ **Last updated:** [August 14, 2026, 3:52pm UTC](https://sierraconnect.protoexpress.com/t/what-s-the-biggest-lie-in-pcb-design/4372 "2026-08-14T15:52:55Z")
“This is the final revision.” --- ## [SPOT THE FLAW: Look beneath the package](https://sierraconnect.protoexpress.com/t/spot-the-flaw-look-beneath-the-package/4357)
**Author:** [@rahuls](https://sierraconnect.protoexpress.com/u/rahuls)\ **Replies:** 1\ **Last updated:** [August 14, 2026, 5:55am UTC](https://sierraconnect.protoexpress.com/t/spot-the-flaw-look-beneath-the-package/4357 "2026-08-14T05:55:04Z")
Answer on Friday --- ## [How do you ensure your PCB design is ready for RoHS-compliant manufacturing?](https://sierraconnect.protoexpress.com/t/how-do-you-ensure-your-pcb-design-is-ready-for-rohs-compliant-manufacturing/4356)
**Author:** [@Zaibahmed\_Mannur](https://sierraconnect.protoexpress.com/u/Zaibahmed_Mannur)\ **Replies:** 2\ **Last updated:** [August 12, 2026, 1:56pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-ensure-your-pcb-design-is-ready-for-rohs-compliant-manufacturing/4356 "2026-08-12T13:56:16Z")
RoHS compliance isn’t something to check only after the PCB is designed. Material selection, surface finish, component requirements, and assembly temperatures can all affect whether a board is ready for lead-free RoHS-co… --- ## [Rigid-Flex Layer Preference](https://sierraconnect.protoexpress.com/t/rigid-flex-layer-preference/4340)
**Author:** [@phil.holden](https://sierraconnect.protoexpress.com/u/phil.holden)\ **Replies:** 3\ **Last updated:** [August 12, 2026, 1:41pm UTC](https://sierraconnect.protoexpress.com/t/rigid-flex-layer-preference/4340 "2026-08-12T13:41:49Z")
For a 2-layer rigid-flex with a single-layer flex limb, do you have a fabrication preference for whether the flex copper continues from the top or bottom rigid layer, or is either acceptable? --- ## [The History of Flexible PCBs and Their Modern Application](https://sierraconnect.protoexpress.com/t/the-history-of-flexible-pcbs-and-their-modern-application/4354)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [August 12, 2026, 12:20pm UTC](https://sierraconnect.protoexpress.com/t/the-history-of-flexible-pcbs-and-their-modern-application/4354 "2026-08-12T12:20:59Z")
Originally published at: https://www.protoexpress.com/blog/the-history-of-flexible-pcbs-and-their-modern-applications/ Modern electronics manufacturers often face contradictory requirements when integrating complex c… --- ## [COURSE: EMC testing by Karen Burnham](https://sierraconnect.protoexpress.com/t/course-emc-testing-by-karen-burnham/4351)
**Author:** [@rahuls](https://sierraconnect.protoexpress.com/u/rahuls)\ **Replies:** 0\ **Last updated:** [August 11, 2026, 2:49pm UTC](https://sierraconnect.protoexpress.com/t/course-emc-testing-by-karen-burnham/4351 "2026-08-11T14:49:00Z")
We recently had the pleasure of hosting Karen Burnham for a full-day seminar on EMC testing, and we didn’t want the learning to stop there. We’ve now turned the recording into an on-demand course on Sierra Academy, so a… [Previous page](https://sierraconnect.protoexpress.com/latest.md) [Next page](https://sierraconnect.protoexpress.com/latest.md?page=2)