# Signal and Power **URL:** https://sierraconnect.protoexpress.com/c/signal-and-power/17.md?page=1 [Latest](https://sierraconnect.protoexpress.com/latest.md) · [Categories](https://sierraconnect.protoexpress.com/categories.md) · [Tags](https://sierraconnect.protoexpress.com/tags.md) **Page:** 2 --- ## [Shielding effectiveness by Karen Burnham](https://sierraconnect.protoexpress.com/t/shielding-effectiveness-by-karen-burnham/2878)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [February 3, 2025, 4:55pm UTC](https://sierraconnect.protoexpress.com/t/shielding-effectiveness-by-karen-burnham/2878 "2025-02-03T16:55:36Z")
Effective shielding is essential for ensuring proper EMC performance, but measuring it correctly can be tricky. @karen.burnham recently highlighted critical concepts for measuring shielding effectiveness, offering pra… --- ## ["There's this thing I call the EMC fire triangle." - Karen Burnham](https://sierraconnect.protoexpress.com/t/theres-this-thing-i-call-the-emc-fire-triangle-karen-burnham/2840)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [January 23, 2025, 4:54pm UTC](https://sierraconnect.protoexpress.com/t/theres-this-thing-i-call-the-emc-fire-triangle-karen-burnham/2840 "2025-01-23T16:54:53Z")
"So there’s a thing I call the EMC fire triangle, and that is, the idea that a lot of us learned as kids that to have a fire, you need three things. You need fuel and you need oxygen and you need a heat source. And if … --- ## [How via impedance impacts signal integrity](https://sierraconnect.protoexpress.com/t/how-via-impedance-impacts-signal-integrity/2815)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [January 16, 2025, 5:38pm UTC](https://sierraconnect.protoexpress.com/t/how-via-impedance-impacts-signal-integrity/2815 "2025-01-16T17:38:45Z")
Via impedance plays a critical role in signal integrity. When the via impedance doesn’t match the transmission line impedance, reflections can occur, with their magnitude depending on the difference at the transition … --- ## ["The signal doesn't flow on a conductor."](https://sierraconnect.protoexpress.com/t/the-signal-doesnt-flow-on-a-conductor/2791)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [January 9, 2025, 4:41pm UTC](https://sierraconnect.protoexpress.com/t/the-signal-doesnt-flow-on-a-conductor/2791 "2025-01-09T16:41:57Z")
“The signal doesn’t flow on a conductor. And your signal is traveling at the rate of roughly about half that of the light, and it’s traveling in the plastic of the circuit board, not in the copper.” Trace Talks EP 6 w… --- ## [How to Pick RF PCB Materials: 6 Important Factors to Consider](https://sierraconnect.protoexpress.com/t/how-to-pick-rf-pcb-materials-6-important-factors-to-consider/1656)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [July 11, 2024, 2:35pm UTC](https://sierraconnect.protoexpress.com/t/how-to-pick-rf-pcb-materials-6-important-factors-to-consider/1656 "2024-07-11T14:35:44Z")
Originally published at: https://www.protoexpress.com/blog/how-to-pick-rf-pcb-materials-important-factors-to-consider/ When designing RF PCBs, selecting the right material is pivotal for achieving optimal board perfo… --- ## [Microwave PCB Design Challenges and How to Overcome Them](https://sierraconnect.protoexpress.com/t/microwave-pcb-design-challenges-and-how-to-overcome-them/2607)
**Author:** [@Pooja\_Mitra](https://sierraconnect.protoexpress.com/u/Pooja_Mitra)\ **Replies:** 4\ **Last updated:** [November 27, 2024, 1:39pm UTC](https://sierraconnect.protoexpress.com/t/microwave-pcb-design-challenges-and-how-to-overcome-them/2607 "2024-11-27T13:39:54Z")
Originally published at: https://www.protoexpress.com/blog/microwave-pcb-design-challenges-and-how-to-overcome-them/ Microwave PCB design presents unique challenges that differ from lower frequency boards. At microwa… --- ## [4 RF PCB Via Design Challenges with Layout Solutions](https://sierraconnect.protoexpress.com/t/4-rf-pcb-via-design-challenges-with-layout-solutions/2681)
**Author:** [@Pooja\_Mitra](https://sierraconnect.protoexpress.com/u/Pooja_Mitra)\ **Replies:** 0\ **Last updated:** [November 26, 2024, 1:14pm UTC](https://sierraconnect.protoexpress.com/t/4-rf-pcb-via-design-challenges-with-layout-solutions/2681 "2024-11-26T13:14:08Z")
Originally published at: https://www.protoexpress.com/blog/rf-pcb-via-design-challenges-with-layout-solutions/ When designing vias for RF PCBs, their impedance should match the desired value in the operating bandwidt… --- ## [10 Best Layout Tips for High-Speed and High-Current PCB Traces](https://sierraconnect.protoexpress.com/t/10-best-layout-tips-for-high-speed-and-high-current-pcb-traces/2651)
**Author:** [@PoulomiG](https://sierraconnect.protoexpress.com/u/PoulomiG)\ **Replies:** 4\ **Last updated:** [November 20, 2024, 6:20am UTC](https://sierraconnect.protoexpress.com/t/10-best-layout-tips-for-high-speed-and-high-current-pcb-traces/2651 "2024-11-20T06:20:54Z")
Originally published at: https://www.protoexpress.com/blog/best-layout-tips-for-high-speed-and-high-current-pcb-traces/ When designing PCBs for frequencies over 5 GHz and current above 2A, trace design becomes paramo… --- ## [7 ways to reduce propagation delay in your PCB design](https://sierraconnect.protoexpress.com/t/7-ways-to-reduce-propagation-delay-in-your-pcb-design/265)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 1\ **Last updated:** [September 19, 2024, 12:14am UTC](https://sierraconnect.protoexpress.com/t/7-ways-to-reduce-propagation-delay-in-your-pcb-design/265 "2024-09-19T00:14:25Z")
How do you reduce your propagation delay? --- ## [11 Best High-Speed PCB Routing Practices](https://sierraconnect.protoexpress.com/t/11-best-high-speed-pcb-routing-practices/163)
**Author:** [@rahuls](https://sierraconnect.protoexpress.com/u/rahuls)\ **Replies:** 6\ **Last updated:** [August 29, 2024, 2:06pm UTC](https://sierraconnect.protoexpress.com/t/11-best-high-speed-pcb-routing-practices/163 "2024-08-29T14:06:43Z")
Originally published at: https://www.protoexpress.com/blog/best-high-speed-pcb-routing-practices/ A PCB designer has a difficult task when it comes to routing a circuit board. Things get a lot more complicated when t… --- ## [Signal Return Paths in a multilayer PCB Stack-Up](https://sierraconnect.protoexpress.com/t/signal-return-paths-in-a-multilayer-pcb-stack-up/1494)
**Author:** [@Criniveran1988](https://sierraconnect.protoexpress.com/u/Criniveran1988)\ **Replies:** 8\ **Last updated:** [July 18, 2024, 3:04pm UTC](https://sierraconnect.protoexpress.com/t/signal-return-paths-in-a-multilayer-pcb-stack-up/1494 "2024-07-18T15:04:31Z")
I am considering the following 6-layer stack-up for a mixed-signal board and would appreciate feedback: Layer 1: Top (Analog signals & components) Layer 2: GND Layer 3: PWR (Supply 1, Supply 2, Supply 3) Layer 4: SIG… --- ## [Power Distribution in a 6-Layer PCB Design](https://sierraconnect.protoexpress.com/t/power-distribution-in-a-6-layer-pcb-design/1167)
**Author:** [@Criniveran1988](https://sierraconnect.protoexpress.com/u/Criniveran1988)\ **Replies:** 7\ **Last updated:** [July 11, 2024, 8:34pm UTC](https://sierraconnect.protoexpress.com/t/power-distribution-in-a-6-layer-pcb-design/1167 "2024-07-11T20:34:39Z")
I’m designing a 6-layer PCB with multiple voltage requirements, including 3.3V, 5V, 12-14V, and 48V. I’m currently deciding on the stack-up configuration to get started with the tracing. I’m considering the best approach… --- ## [Impedance Matching and Power Consumption in Digital Interfaces](https://sierraconnect.protoexpress.com/t/impedance-matching-and-power-consumption-in-digital-interfaces/1401)
**Author:** [@mark](https://sierraconnect.protoexpress.com/u/mark)\ **Replies:** 7\ **Last updated:** [June 28, 2024, 2:29pm UTC](https://sierraconnect.protoexpress.com/t/impedance-matching-and-power-consumption-in-digital-interfaces/1401 "2024-06-28T14:29:57Z")
I’ve been exploring the concept of impedance matching in transmission lines and the role it plays in reducing reflections and power loss. It’s clear that using termination resistors to match the impedance of the transmis… --- ## [Lowering Power Consumption in Digital Interfaces](https://sierraconnect.protoexpress.com/t/lowering-power-consumption-in-digital-interfaces/1031)
**Author:** [@George](https://sierraconnect.protoexpress.com/u/George)\ **Replies:** 3\ **Last updated:** [May 17, 2024, 1:14pm UTC](https://sierraconnect.protoexpress.com/t/lowering-power-consumption-in-digital-interfaces/1031 "2024-05-17T13:14:39Z")
I know why we match the impedance while terminating a transmission line. However, digital interfaces use quite low impedance transmission lines like 100 Ohm in Ethernet communication. Is it possible to lower the power c… --- ## [Noise concerns with SPI bus routed through vias](https://sierraconnect.protoexpress.com/t/noise-concerns-with-spi-bus-routed-through-vias/1214)
**Author:** [@Charles](https://sierraconnect.protoexpress.com/u/Charles)\ **Replies:** 3\ **Last updated:** [May 14, 2024, 2:15pm UTC](https://sierraconnect.protoexpress.com/t/noise-concerns-with-spi-bus-routed-through-vias/1214 "2024-05-14T14:15:17Z")
I’m curious about the impact of routing high-speed signals, such as an SPI bus clocked at 4MHz, through PCB vias. I’ve observed significant noise (±350mV) on my SPI bus signals, which operate at 3.3V levels. Despite the… --- ## [Impact of Via Stitching on PCB EMI](https://sierraconnect.protoexpress.com/t/impact-of-via-stitching-on-pcb-emi/1219)
**Author:** [@Henry](https://sierraconnect.protoexpress.com/u/Henry)\ **Replies:** 3\ **Last updated:** [May 2, 2024, 7:57pm UTC](https://sierraconnect.protoexpress.com/t/impact-of-via-stitching-on-pcb-emi/1219 "2024-05-02T19:57:50Z")
I’ve been exploring the concept of via stitching for the ground planes surrounding the perimeter of my PCB. While researching, I’ve found various resources suggesting guidelines like maintaining a specific spacing distan… --- ## [Copper Pour Considerations](https://sierraconnect.protoexpress.com/t/copper-pour-considerations/1282)
**Author:** [@mark](https://sierraconnect.protoexpress.com/u/mark)\ **Replies:** 5\ **Last updated:** [May 2, 2024, 7:47pm UTC](https://sierraconnect.protoexpress.com/t/copper-pour-considerations/1282 "2024-05-02T19:47:20Z")
I’m currently working on designing a power distribution board to accommodate up to four ESC controllers, each drawing a continuous current of 40 A (totaling 160 A) from a single LiPo battery. Additionally, this board wil… --- ## [5 PCB Trace Termination Techniques to Reduce Signal Reflections](https://sierraconnect.protoexpress.com/t/5-pcb-trace-termination-techniques-to-reduce-signal-reflections/1358)
**Author:** [@PoulomiG](https://sierraconnect.protoexpress.com/u/PoulomiG)\ **Replies:** 2\ **Last updated:** [April 25, 2024, 4:01am UTC](https://sierraconnect.protoexpress.com/t/5-pcb-trace-termination-techniques-to-reduce-signal-reflections/1358 "2024-04-25T04:01:13Z")
Originally published at: https://www.protoexpress.com/blog/pcb-trace-termination-techniques-to-reduce-signal-reflections/ PCB trace termination is crucial for maintaining signal integrity in your designs. Unterminate… --- ## [4 Common PDN Design Challenges and How to Resolve Them](https://sierraconnect.protoexpress.com/t/4-common-pdn-design-challenges-and-how-to-resolve-them/1193)
**Author:** [@Pooja\_Mitra](https://sierraconnect.protoexpress.com/u/Pooja_Mitra)\ **Replies:** 8\ **Last updated:** [April 4, 2024, 5:29am UTC](https://sierraconnect.protoexpress.com/t/4-common-pdn-design-challenges-and-how-to-resolve-them/1193 "2024-04-04T05:29:04Z")
Originally published at: https://www.protoexpress.com/blog/common-pdn-design-challenges-and-how-to-resolve/ An efficient PDN design in PCBs ensures a stable power supply and consistent voltage levels across all compo… --- ## [Return Current Path in High-Speed PCB Designs](https://sierraconnect.protoexpress.com/t/return-current-path-in-high-speed-pcb-designs/1196)
**Author:** [@Fen](https://sierraconnect.protoexpress.com/u/Fen)\ **Replies:** 5\ **Last updated:** [March 25, 2024, 9:31pm UTC](https://sierraconnect.protoexpress.com/t/return-current-path-in-high-speed-pcb-designs/1196 "2024-03-25T21:31:02Z")
Hi, I’m working on a high-speed PCB design and have a question about the return current path for the signal. It’s widely acknowledged that high-speed signals create a return current path on the plane directly beneath th… --- ## [Considerations for Traces Near board Edges](https://sierraconnect.protoexpress.com/t/considerations-for-traces-near-board-edges/1205)
**Author:** [@mark](https://sierraconnect.protoexpress.com/u/mark)\ **Replies:** 3\ **Last updated:** [March 20, 2024, 3:52pm UTC](https://sierraconnect.protoexpress.com/t/considerations-for-traces-near-board-edges/1205 "2024-03-20T15:52:32Z")
Is there a specific reason why traces shouldn’t be placed close to the edge of the PCB, whether it’s an electrical concern or a mechanical issue related to potential trace damage during board cutting? When routing high-… --- ## [PCB routing](https://sierraconnect.protoexpress.com/t/pcb-routing/864)
**Author:** [@Olivia](https://sierraconnect.protoexpress.com/u/Olivia)\ **Replies:** 2\ **Last updated:** [February 26, 2024, 3:18pm UTC](https://sierraconnect.protoexpress.com/t/pcb-routing/864 "2024-02-26T15:18:12Z")
Can I route two different impedance profile traces, for example, 50 ohm SE and 90 ohm SE, on the same layer? --- ## [Signal Termination Strategies](https://sierraconnect.protoexpress.com/t/signal-termination-strategies/943)
**Author:** [@Olivia](https://sierraconnect.protoexpress.com/u/Olivia)\ **Replies:** 2\ **Last updated:** [February 21, 2024, 2:16pm UTC](https://sierraconnect.protoexpress.com/t/signal-termination-strategies/943 "2024-02-21T14:16:55Z")
What strategies do you implement for signal termination at receiver and transmitter ends in high-speed digital interfaces? --- ## [Calculating L and C Components](https://sierraconnect.protoexpress.com/t/calculating-l-and-c-components/990)
**Author:** [@johnkl](https://sierraconnect.protoexpress.com/u/johnkl)\ **Replies:** 1\ **Last updated:** [February 5, 2024, 6:49pm UTC](https://sierraconnect.protoexpress.com/t/calculating-l-and-c-components/990 "2024-02-05T18:49:24Z")
I have noticed many times that an antenna has matching circuits with L(inductor) and C(capacitor) components. How do I calculate the L and C values for 2.4 GHz transmission frequency? --- ## [Reduce power consumption using high impedance transmission lines](https://sierraconnect.protoexpress.com/t/reduce-power-consumption-using-high-impedance-transmission-lines/979)
**Author:** [@Rilley](https://sierraconnect.protoexpress.com/u/Rilley)\ **Replies:** 1\ **Last updated:** [February 2, 2024, 7:13pm UTC](https://sierraconnect.protoexpress.com/t/reduce-power-consumption-using-high-impedance-transmission-lines/979 "2024-02-02T19:13:01Z")
Is it possible to decrease power consumption in digital interfaces by employing high impedance transmission lines? --- ## [Case study: Designing Microcontroller and Functional PCBs with Antenna](https://sierraconnect.protoexpress.com/t/case-study-designing-microcontroller-and-functional-pcbs-with-antenna/965)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [January 31, 2024, 12:10pm UTC](https://sierraconnect.protoexpress.com/t/case-study-designing-microcontroller-and-functional-pcbs-with-antenna/965 "2024-01-31T12:10:12Z")
Originally published at: https://www.protoexpress.com/blog/case-study-designing-microcontroller-and-functional-pcbs-with-antenna/ We recently worked on a PCB design comprising 2 modules. Module 1 has a microcontrolle… --- ## [USB differential pair routing](https://sierraconnect.protoexpress.com/t/usb-differential-pair-routing/957)
**Author:** [@Rachel](https://sierraconnect.protoexpress.com/u/Rachel)\ **Replies:** 1\ **Last updated:** [January 29, 2024, 11:37pm UTC](https://sierraconnect.protoexpress.com/t/usb-differential-pair-routing/957 "2024-01-29T23:37:20Z")
Do we need to do impedance control for laying out USB differential routing in a 50mm x 50mm PCB? --- ## [Impedance calculation](https://sierraconnect.protoexpress.com/t/impedance-calculation/907)
**Author:** [@Jane](https://sierraconnect.protoexpress.com/u/Jane)\ **Replies:** 1\ **Last updated:** [January 22, 2024, 8:51pm UTC](https://sierraconnect.protoexpress.com/t/impedance-calculation/907 "2024-01-22T20:51:30Z")
Does the presence of solder mask on PCBs impact impedance calculations, and is it important to take into account the effects of conformal coating while carrying out impedance calculations? --- ## [Samtec Signal Integrity Handbook](https://sierraconnect.protoexpress.com/t/samtec-signal-integrity-handbook/888)
**Author:** [@ConnectorGuy](https://sierraconnect.protoexpress.com/u/ConnectorGuy)\ **Replies:** 5\ **Last updated:** [January 18, 2024, 7:29am UTC](https://sierraconnect.protoexpress.com/t/samtec-signal-integrity-handbook/888 "2024-01-18T07:29:38Z")
Samtec and several other thought leaders in this ecosystem know that SI 101 questions stumble many engineers and make highs-speed digital design. Samtec’s SI Handbook demystifies basic SI priciples that many learn about… --- ## [Ask your PI questions to Steve Sandler](https://sierraconnect.protoexpress.com/t/ask-your-pi-questions-to-steve-sandler/235)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 1\ **Last updated:** [January 17, 2024, 9:36pm UTC](https://sierraconnect.protoexpress.com/t/ask-your-pi-questions-to-steve-sandler/235 "2024-01-17T21:36:03Z")
Don’t forget to ask your questions about power integrity in this thread: [Previous page](https://sierraconnect.protoexpress.com/c/signal-and-power/17.md) [Next page](https://sierraconnect.protoexpress.com/c/signal-and-power/17.md?page=2)