# Design and Layout **URL:** https://sierraconnect.protoexpress.com/c/design-and-layout/5.md?page=2 [Latest](https://sierraconnect.protoexpress.com/latest.md) · [Categories](https://sierraconnect.protoexpress.com/categories.md) · [Tags](https://sierraconnect.protoexpress.com/tags.md) **Page:** 3 --- ## [When do you choose an HDI PCB stack-up over a standard one?](https://sierraconnect.protoexpress.com/t/when-do-you-choose-an-hdi-pcb-stack-up-over-a-standard-one/3872)
**Author:** [@Pooja\_Mitra](https://sierraconnect.protoexpress.com/u/Pooja_Mitra)\ **Replies:** 2\ **Last updated:** [February 18, 2026, 1:59pm UTC](https://sierraconnect.protoexpress.com/t/when-do-you-choose-an-hdi-pcb-stack-up-over-a-standard-one/3872 "2026-02-18T13:59:06Z")
One of the most common queries we receive from designers is: how do I know if my design requires HDI or standard build-up? This usually comes up when routing starts getting tight or when a fine-pitch BGA enters the … --- ## [How and when do you decide to use via filling in your PCB designs?](https://sierraconnect.protoexpress.com/t/how-and-when-do-you-decide-to-use-via-filling-in-your-pcb-designs/3860)
**Author:** [@Sushmitha](https://sierraconnect.protoexpress.com/u/Sushmitha)\ **Replies:** 2\ **Last updated:** [February 11, 2026, 11:19am UTC](https://sierraconnect.protoexpress.com/t/how-and-when-do-you-decide-to-use-via-filling-in-your-pcb-designs/3860 "2026-02-11T11:19:12Z")
We see a lot of questions around via filling strategies during layout and fabrication reviews, especially on HDI boards, BGAs, and designs targeting high-reliability assembly. I thought it would be useful to start a conv… --- ## [How do you decide the trace width for your PCB designs?](https://sierraconnect.protoexpress.com/t/how-do-you-decide-the-trace-width-for-your-pcb-designs/3848)
**Author:** [@PoulomiG](https://sierraconnect.protoexpress.com/u/PoulomiG)\ **Replies:** 2\ **Last updated:** [February 4, 2026, 11:27am UTC](https://sierraconnect.protoexpress.com/t/how-do-you-decide-the-trace-width-for-your-pcb-designs/3848 "2026-02-04T11:27:31Z")
We often see questions about trace width selection during layout reviews, so I wanted to start a conversation here on how designers determine trace width in different scenarios. Trace width determines both current-carry… --- ## [How to bring onboard LED indicators to an enclosure exterior](https://sierraconnect.protoexpress.com/t/how-to-bring-onboard-led-indicators-to-an-enclosure-exterior/3808)
**Author:** [@anderson](https://sierraconnect.protoexpress.com/u/anderson)\ **Replies:** 5\ **Last updated:** [February 3, 2026, 5:05pm UTC](https://sierraconnect.protoexpress.com/t/how-to-bring-onboard-led-indicators-to-an-enclosure-exterior/3808 "2026-02-03T17:05:44Z")
I have a PCB mounted inside an enclosure with onboard LEDs for status indication. The LEDs aren’t visible from outside. What are the most reliable techniques to bring the LED outside of a sealed enclosure --- ## [How to quantify copper balance between PCB Layers](https://sierraconnect.protoexpress.com/t/how-to-quantify-copper-balance-between-pcb-layers/3815)
**Author:** [@mark](https://sierraconnect.protoexpress.com/u/mark)\ **Replies:** 4\ **Last updated:** [January 30, 2026, 3:16pm UTC](https://sierraconnect.protoexpress.com/t/how-to-quantify-copper-balance-between-pcb-layers/3815 "2026-01-30T15:16:16Z")
It’s common practice to balance copper between the top and bottom layers of a PCB to reduce warpage and fabrication issues. Is there a practical way to quantify copper balance (for example, percentage coverage per layer… --- ## [How do you decide and specify controlled impedance in your PCB designs?](https://sierraconnect.protoexpress.com/t/how-do-you-decide-and-specify-controlled-impedance-in-your-pcb-designs/3831)
**Author:** [@milan](https://sierraconnect.protoexpress.com/u/milan)\ **Replies:** 3\ **Last updated:** [January 28, 2026, 9:27am UTC](https://sierraconnect.protoexpress.com/t/how-do-you-decide-and-specify-controlled-impedance-in-your-pcb-designs/3831 "2026-01-28T09:27:44Z")
We encounter impedance management questions frequently during DFM and layout reviews, especially for high-speed designs. I wanted to start a thread here on how designers determine and document controlled impedance requir… --- ## [How do you determine your solder mask clearance?](https://sierraconnect.protoexpress.com/t/how-do-you-determine-your-solder-mask-clearance/3821)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 3\ **Last updated:** [January 22, 2026, 2:20pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-determine-your-solder-mask-clearance/3821 "2026-01-22T14:20:05Z")
We often see solder mask clearance violations during DFM checks, especially on dense boards and fine-pitch components, so it would be useful to start a discussion here on how designers decide the right solder mask cleara… --- ## [How do decide the size of your annular ring?](https://sierraconnect.protoexpress.com/t/how-do-decide-the-size-of-your-annular-ring/3820)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 3\ **Last updated:** [January 22, 2026, 5:24am UTC](https://sierraconnect.protoexpress.com/t/how-do-decide-the-size-of-your-annular-ring/3820 "2026-01-22T05:24:40Z")
We often this issue when running DFM checks so I thought of starting a conversation here on the topic of annular ring size. Quick recap on annular ring requirements: the minimum annular ring width should always meet or … --- ## [AC Power line Trace width, clearance and creepage](https://sierraconnect.protoexpress.com/t/ac-power-line-trace-width-clearance-and-creepage/3779)
**Author:** [@shyammarimuthu123](https://sierraconnect.protoexpress.com/u/shyammarimuthu123)\ **Replies:** 2\ **Last updated:** [January 20, 2026, 3:28pm UTC](https://sierraconnect.protoexpress.com/t/ac-power-line-trace-width-clearance-and-creepage/3779 "2026-01-20T15:28:46Z")
Hi friends, I want to know what should be the trace width for 1A and 2A @ 230VAC supply, whether i can follow the same trace width as DC --- ## [The Pros and Cons of a Composite Amplifier for PCB Designers](https://sierraconnect.protoexpress.com/t/the-pros-and-cons-of-a-composite-amplifier-for-pcb-designers/3809)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [January 15, 2026, 3:19pm UTC](https://sierraconnect.protoexpress.com/t/the-pros-and-cons-of-a-composite-amplifier-for-pcb-designers/3809 "2026-01-15T15:19:25Z")
Originally published at: https://www.protoexpress.com/blog/composite-amplifiers-the-good-and-the-bad/ Several manufacturers are making serious efforts in widening the scope of composite amplifiers. The key features o… --- ## [How's AI Transforming the Circuit Board Industry?](https://sierraconnect.protoexpress.com/t/hows-ai-transforming-the-circuit-board-industry/3802)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [January 14, 2026, 5:20pm UTC](https://sierraconnect.protoexpress.com/t/hows-ai-transforming-the-circuit-board-industry/3802 "2026-01-14T17:20:19Z")
Originally published at: https://www.protoexpress.com/blog/hows-ai-transforming-circuit-board-industry/ AI-assisted circuit board design is reshaping the schematic and layout creation process by recommending optimal … --- ## [Building footprints using bottom-view drawings](https://sierraconnect.protoexpress.com/t/building-footprints-using-bottom-view-drawings/3784)
**Author:** [@anderson](https://sierraconnect.protoexpress.com/u/anderson)\ **Replies:** 6\ **Last updated:** [January 13, 2026, 2:57pm UTC](https://sierraconnect.protoexpress.com/t/building-footprints-using-bottom-view-drawings/3784 "2026-01-13T14:57:28Z")
I’m creating a footprint, RDE03 Series DC/DC converter. The datasheet shows the pin layout as a bottom view (left). When building the footprint in my EDA tool, does this mean the pin arrangement needs to be mirrored (fo… --- ## [Metal pcbs](https://sierraconnect.protoexpress.com/t/metal-pcbs/3514)
**Author:** [@joseph.witkowski](https://sierraconnect.protoexpress.com/u/joseph.witkowski)\ **Replies:** 8\ **Last updated:** [December 24, 2025, 5:54pm UTC](https://sierraconnect.protoexpress.com/t/metal-pcbs/3514 "2025-12-24T17:54:56Z")
I was wondering if with single layer metal PCBs, can the PCB be built so that 1/8” of the border around the edge of the PCB and the mounting holes can be free of copper, soldermask, and Tpreg so that only the exposed alu… --- ## [Feasibility of using a non-plated counterbored mounting holes on 2-Layer board](https://sierraconnect.protoexpress.com/t/feasibility-of-using-a-non-plated-counterbored-mounting-holes-on-2-layer-board/3705)
**Author:** [@johnkl](https://sierraconnect.protoexpress.com/u/johnkl)\ **Replies:** 4\ **Last updated:** [December 11, 2025, 3:20am UTC](https://sierraconnect.protoexpress.com/t/feasibility-of-using-a-non-plated-counterbored-mounting-holes-on-2-layer-board/3705 "2025-12-11T03:20:11Z")
I’m considering using non-plated counterbored mounting holes on a low-cost 2-layer FR4 board (62mil thickness) board with 120 mil drill / 187 mil counterbore OD / 25mil counterbore depth How common is this feature on co… --- ## [Surface Finish Choice for Contact Pads](https://sierraconnect.protoexpress.com/t/surface-finish-choice-for-contact-pads/3719)
**Author:** [@johnkl](https://sierraconnect.protoexpress.com/u/johnkl)\ **Replies:** 8\ **Last updated:** [December 5, 2025, 3:09pm UTC](https://sierraconnect.protoexpress.com/t/surface-finish-choice-for-contact-pads/3719 "2025-12-05T15:09:21Z")
I have two charging pads in the middle of a PCB that mate repeatedly with pogo pins. Worried about ENIG wearing out. Can fabs do selective hard gold on interior pads, or is that generally done on edge connectors? --- ## [When to use Immersion Silver (ImAg) surface finish](https://sierraconnect.protoexpress.com/t/when-to-use-immersion-silver-imag-surface-finish/3689)
**Author:** [@Rilley](https://sierraconnect.protoexpress.com/u/Rilley)\ **Replies:** 6\ **Last updated:** [November 24, 2025, 3:14pm UTC](https://sierraconnect.protoexpress.com/t/when-to-use-immersion-silver-imag-surface-finish/3689 "2025-11-24T15:14:37Z")
I’m planning to use Immersion Silver (ImAg) in automotive environments. I’m aware that it can be affected by sulfur exposure, but I haven’t found solid references or field reports on actual reliability problems. Assumin… --- ## [Trace under the passive components is allowed? is any IPC standard specify this point](https://sierraconnect.protoexpress.com/t/trace-under-the-passive-components-is-allowed-is-any-ipc-standard-specify-this-point/3710)
**Author:** [@kabaleeswaran.kr](https://sierraconnect.protoexpress.com/u/kabaleeswaran.kr)\ **Replies:** 1\ **Last updated:** [November 21, 2025, 8:08pm UTC](https://sierraconnect.protoexpress.com/t/trace-under-the-passive-components-is-allowed-is-any-ipc-standard-specify-this-point/3710 "2025-11-21T20:08:13Z")
Hi Team, I reviewed the layout; the product will be followed as IPC -class 3 standard. I found some traces are routed under the passive components. In general, I will avoid routing under the passive components like resi… --- ## [PCB Solder Mask Clearance Every Engineer Should Know](https://sierraconnect.protoexpress.com/t/pcb-solder-mask-clearance-every-engineer-should-know/3704)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [November 18, 2025, 2:04pm UTC](https://sierraconnect.protoexpress.com/t/pcb-solder-mask-clearance-every-engineer-should-know/3704 "2025-11-18T14:04:54Z")
Originally published at: https://www.protoexpress.com/blog/pcb-solder-mask-clearance-every-engineer-should-know/ PCB solder mask clearance is the space between a copper pad and the surrounding solder resist. It typic… --- ## [PCB Surface Finishes and Their Use Cases](https://sierraconnect.protoexpress.com/t/pcb-surface-finishes-and-their-use-cases/3703)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [November 18, 2025, 1:09pm UTC](https://sierraconnect.protoexpress.com/t/pcb-surface-finishes-and-their-use-cases/3703 "2025-11-18T13:09:20Z")
A PCB surface finish is a thin protective coating applied to the exposed copper areas, such as pads, traces, and vias, to prevent oxidation and corrosion. This coating ensures good solderability during assembly and ma… --- ## [Do Fabricators Need Drill Maps on Fab Drawings?](https://sierraconnect.protoexpress.com/t/do-fabricators-need-drill-maps-on-fab-drawings/3667)
**Author:** [@johnkl](https://sierraconnect.protoexpress.com/u/johnkl)\ **Replies:** 7\ **Last updated:** [November 10, 2025, 1:58pm UTC](https://sierraconnect.protoexpress.com/t/do-fabricators-need-drill-maps-on-fab-drawings/3667 "2025-11-10T13:58:13Z")
When creating a PCB fabrication drawing, how important is it to include a drill map. A drill table makes sense for verifying hole counts and min/max sizes, but the map itself, is it necessary and do fabricator still requ… --- ## [The cost implications of HDI vs higher layer count](https://sierraconnect.protoexpress.com/t/the-cost-implications-of-hdi-vs-higher-layer-count/3679)
**Author:** [@broy](https://sierraconnect.protoexpress.com/u/broy)\ **Replies:** 1\ **Last updated:** [November 7, 2025, 3:44am UTC](https://sierraconnect.protoexpress.com/t/the-cost-implications-of-hdi-vs-higher-layer-count/3679 "2025-11-07T03:44:20Z")
I am working on a relatively large board 20-30in^2 and I want to understand the cost difference between a 12 layer HDI and a 16 layer standard pcb. Beyond that I am interested to understand general cost per layer and the… --- ## [Should vias be tented on one side or both?](https://sierraconnect.protoexpress.com/t/should-vias-be-tented-on-one-side-or-both/3637)
**Author:** [@mark](https://sierraconnect.protoexpress.com/u/mark)\ **Replies:** 9\ **Last updated:** [October 28, 2025, 3:24pm UTC](https://sierraconnect.protoexpress.com/t/should-vias-be-tented-on-one-side-or-both/3637 "2025-10-28T15:24:55Z")
What is the best practice for tenting vias? Is it only one side or both. I used to know that tenting should be done on only one side to allow outgassing and avoid trapped air during reflow. But I heard the opposite recom… --- ## [What Causes High-Leakage Current in PCBs and How to Prevent It?](https://sierraconnect.protoexpress.com/t/what-causes-high-leakage-current-in-pcbs-and-how-to-prevent-it/3662)
**Author:** [@Pooja\_Mitra](https://sierraconnect.protoexpress.com/u/Pooja_Mitra)\ **Replies:** 0\ **Last updated:** [October 28, 2025, 2:52pm UTC](https://sierraconnect.protoexpress.com/t/what-causes-high-leakage-current-in-pcbs-and-how-to-prevent-it/3662 "2025-10-28T14:52:43Z")
Originally published at: https://www.protoexpress.com/blog/what-causes-high-leakage-current-in-pcbs-how-to-prevent-it/ High-leakage current in PCBs is caused by moisture absorption and inadequate creepage and clearan… --- ## [Ground Plane Strategy for a 2-Layer PCB from an EMI/EMC Perspective](https://sierraconnect.protoexpress.com/t/ground-plane-strategy-for-a-2-layer-pcb-from-an-emi-emc-perspective/3630)
**Author:** [@Rachel](https://sierraconnect.protoexpress.com/u/Rachel)\ **Replies:** 5\ **Last updated:** [October 20, 2025, 7:17pm UTC](https://sierraconnect.protoexpress.com/t/ground-plane-strategy-for-a-2-layer-pcb-from-an-emi-emc-perspective/3630 "2025-10-20T19:17:44Z")
I’m designing a 2-layer PCB where the top layer is densely packed with through-hole and surface-mount components, while the bottom layer has minimal routing. From an EMI/EMC perspective, which ground plane strategy would… --- ## [Best practices for using ground pours on 4-layer PCBs with internal planes](https://sierraconnect.protoexpress.com/t/best-practices-for-using-ground-pours-on-4-layer-pcbs-with-internal-planes/3624)
**Author:** [@Sophia](https://sierraconnect.protoexpress.com/u/Sophia)\ **Replies:** 3\ **Last updated:** [October 10, 2025, 12:58pm UTC](https://sierraconnect.protoexpress.com/t/best-practices-for-using-ground-pours-on-4-layer-pcbs-with-internal-planes/3624 "2025-10-10T12:58:08Z")
I’m designing a 4-layer PCB where the two inner layers are solid ground planes, and the outer layers carry signals. Since I’ve always added ground pours on 2-layer designs, I’m wondering should I still add ground pours w… --- ## [Best practices for grounding USB/high-speed cable shields](https://sierraconnect.protoexpress.com/t/best-practices-for-grounding-usb-high-speed-cable-shields/3579)
**Author:** [@mark](https://sierraconnect.protoexpress.com/u/mark)\ **Replies:** 4\ **Last updated:** [October 7, 2025, 4:18pm UTC](https://sierraconnect.protoexpress.com/t/best-practices-for-grounding-usb-high-speed-cable-shields/3579 "2025-10-07T16:18:45Z")
For USB or high-speed interfaces, is it better to connect the cable shield directly to PCB ground or through a filtering element such as a ferrite bead? --- ## [Best Practices for Tying Digital, Analog, and Chassis Grounds in Mixed-Signal PCBs](https://sierraconnect.protoexpress.com/t/best-practices-for-tying-digital-analog-and-chassis-grounds-in-mixed-signal-pcbs/3596)
**Author:** [@Rilley](https://sierraconnect.protoexpress.com/u/Rilley)\ **Replies:** 7\ **Last updated:** [October 6, 2025, 2:20pm UTC](https://sierraconnect.protoexpress.com/t/best-practices-for-tying-digital-analog-and-chassis-grounds-in-mixed-signal-pcbs/3596 "2025-10-06T14:20:44Z")
What are the current best practices for connecting digital ground, analog ground, and chassis ground in mixed-signal PCBs? --- ## [PCB for 230 VAC @ 8 A — Please Check My Understanding](https://sierraconnect.protoexpress.com/t/pcb-for-230-vac-8-a-please-check-my-understanding/3605)
**Author:** [@rayansayedpd](https://sierraconnect.protoexpress.com/u/rayansayedpd)\ **Replies:** 1\ **Last updated:** [September 29, 2025, 6:35pm UTC](https://sierraconnect.protoexpress.com/t/pcb-for-230-vac-8-a-please-check-my-understanding/3605 "2025-09-29T18:35:25Z")
Hi everyone, I’m designing a PCB that will switch 230 VAC at about 8 A using a relay. I’m still learning and would like to check if my understanding is correct: Trace width: At 50 Hz (mains), skin effect is negligib… --- ## [How to Reduce Ground Bounce in PCB Assembly](https://sierraconnect.protoexpress.com/t/how-to-reduce-ground-bounce-in-pcb-assembly/3604)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [September 29, 2025, 2:00pm UTC](https://sierraconnect.protoexpress.com/t/how-to-reduce-ground-bounce-in-pcb-assembly/3604 "2025-09-29T14:00:02Z")
Originally published at: https://www.protoexpress.com/blog/how-to-reduce-ground-bounce-pcba/ Ground bounce is a source of noise in a PCB assembly. It is important to prevent this as it interrupts high-speed or high-f… --- ## [PCB designer is asking for some of the math behind "the signal is in the field"](https://sierraconnect.protoexpress.com/t/pcb-designer-is-asking-for-some-of-the-math-behind-the-signal-is-in-the-field/3576)
**Author:** [@minertom11551](https://sierraconnect.protoexpress.com/u/minertom11551)\ **Replies:** 7\ **Last updated:** [September 26, 2025, 8:00pm UTC](https://sierraconnect.protoexpress.com/t/pcb-designer-is-asking-for-some-of-the-math-behind-the-signal-is-in-the-field/3576 "2025-09-26T20:00:00Z")
Hi, I have the books by Archambeault, Ott, Morrison, Young and countless application notes. I can recite Maxwell’s equations by heart and I know of the Telegraphers equations. However, I would like, if someone can poin… [Previous page](https://sierraconnect.protoexpress.com/c/design-and-layout/5.md?page=1) [Next page](https://sierraconnect.protoexpress.com/c/design-and-layout/5.md?page=3)