# Design and Layout **URL:** https://sierraconnect.protoexpress.com/c/design-and-layout/5.md [Latest](https://sierraconnect.protoexpress.com/latest.md) · [Categories](https://sierraconnect.protoexpress.com/categories.md) · [Tags](https://sierraconnect.protoexpress.com/tags.md) --- ## [About the Design and Layout category](https://sierraconnect.protoexpress.com/t/about-the-design-and-layout-category/13)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0
This category is for users who seek help or wish to share their experience with PCB design and layout. Our subcategories are: Beginner’s corner Design tools and software Schematic and layout Design for Manufacturing D… --- ## [DDR4 Layout Review for AMD/Xilinix Ultrascale](https://sierraconnect.protoexpress.com/t/ddr4-layout-review-for-amd-xilinix-ultrascale/4589)
**Author:** [@harshitshakya49](https://sierraconnect.protoexpress.com/u/harshitshakya49)\ **Replies:** 4\ **Last updated:** [October 22, 2026, 4:52pm UTC](https://sierraconnect.protoexpress.com/t/ddr4-layout-review-for-amd-xilinix-ultrascale/4589 "2026-10-22T16:52:34Z")
Hello Sierra Circuits Community, I am reviewing a DDR4 design using an AMD/Xilinx UltraScale FPGA. Our PCB layout includes net-ties based on the reference design, and I would like to confirm whether they are needed. De… --- ## [Routing Diff Pairs? 5 Things to Consider](https://sierraconnect.protoexpress.com/t/routing-diff-pairs-5-things-to-consider/4575)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [October 12, 2026, 12:58pm UTC](https://sierraconnect.protoexpress.com/t/routing-diff-pairs-5-things-to-consider/4575 "2026-10-12T12:58:43Z")
Differential pairs transmit data using two complementary signals. To preserve signal quality during transmission, PCB designers must account for factors such as impedance variations, uneven spacing, excessive skew, an… --- ## [DFA mistakes we keep seeing](https://sierraconnect.protoexpress.com/t/dfa-mistakes-we-keep-seeing/4509)
**Author:** [@atar.mittal](https://sierraconnect.protoexpress.com/u/atar.mittal)\ **Replies:** 0\ **Last updated:** [September 22, 2026, 4:21pm UTC](https://sierraconnect.protoexpress.com/t/dfa-mistakes-we-keep-seeing/4509 "2026-09-22T16:21:47Z")
Our PCB house has seen plenty of boards that were perfectly manufacturable… until it was time to assemble them. A few DFA mistakes that cause more trouble than they should: Components placed too close to the board edg… --- ## [How a Multi-Board LED Prototype was Reverse-Engineered into a Single PCB](https://sierraconnect.protoexpress.com/t/how-a-multi-board-led-prototype-was-reverse-engineered-into-a-single-pcb/4494)
**Author:** [@Pooja\_Mitra](https://sierraconnect.protoexpress.com/u/Pooja_Mitra)\ **Replies:** 0\ **Last updated:** [September 17, 2026, 2:07pm UTC](https://sierraconnect.protoexpress.com/t/how-a-multi-board-led-prototype-was-reverse-engineered-into-a-single-pcb/4494 "2026-09-17T14:07:15Z")
Originally published at: How a Multi-Board LED was Reverse-Engineered | Sierra Circuits Sierra Circuits reverse-engineered an LED controller prototype with multiple off-the-shelf modules and consolidated the design i… --- ## [6 PCB Thermal Management Guidelines for Designers](https://sierraconnect.protoexpress.com/t/6-pcb-thermal-management-guidelines-for-designers/4444)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [September 8, 2026, 1:08pm UTC](https://sierraconnect.protoexpress.com/t/6-pcb-thermal-management-guidelines-for-designers/4444 "2026-09-08T13:08:59Z")
Thermal management in PCBs is a crucial design aspect, especially in high-power designs where components and conductors generate significant heat during operation. Excessive temperature can increase electrical resista… --- ## [PCB Manufacturing Inquiry – 0.15 mm Microvias, Buried Vias and Mech through-hole Vias](https://sierraconnect.protoexpress.com/t/pcb-manufacturing-inquiry-0-15-mm-microvias-buried-vias-and-mech-through-hole-vias/4384)
**Author:** [@jjiang](https://sierraconnect.protoexpress.com/u/jjiang)\ **Replies:** 6\ **Last updated:** [August 24, 2026, 3:51pm UTC](https://sierraconnect.protoexpress.com/t/pcb-manufacturing-inquiry-0-15-mm-microvias-buried-vias-and-mech-through-hole-vias/4384 "2026-08-24T15:51:18Z")
I would like to ask about Sierra manufacturing capability for a 10-layer PCB with 0.15 mm microvias, buried vias and through-hole PTHs. I want to design a PCB that is 1.6 mm thick and has a BGA requiring fan-out. The vi… --- ## [Design Considerations for LPDDR4/LPDDR5 Signal Probing](https://sierraconnect.protoexpress.com/t/design-considerations-for-lpddr4-lpddr5-signal-probing/4321)
**Author:** [@harshitshakya49](https://sierraconnect.protoexpress.com/u/harshitshakya49)\ **Replies:** 2\ **Last updated:** [July 30, 2026, 1:36pm UTC](https://sierraconnect.protoexpress.com/t/design-considerations-for-lpddr4-lpddr5-signal-probing/4321 "2026-07-30T13:36:09Z")
Hi everyone, We are designing two different boards: - Board 1: LPDDR4 - Board 2: LPDDR5 For both boards, we need to perform signal probing during hardware validation and debugging. I would like to know the recommend… --- ## [How to Design High-Power PCBs for Better Fabrication and Assembly](https://sierraconnect.protoexpress.com/t/how-to-design-high-power-pcbs-for-better-fabrication-and-assembly/4284)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [July 22, 2026, 4:40pm UTC](https://sierraconnect.protoexpress.com/t/how-to-design-high-power-pcbs-for-better-fabrication-and-assembly/4284 "2026-07-22T16:40:29Z")
Originally published at: https://www.protoexpress.com/blog/how-to-design-high-power-pcbs-for-better-fabrication-and-assembly/ Designing high-power PCBs with fabrication and assembly in mind will make your manufacture… --- ## [Why do impedance mismatches cause signal reflections on PCB transmission lines?](https://sierraconnect.protoexpress.com/t/why-do-impedance-mismatches-cause-signal-reflections-on-pcb-transmission-lines/4233)
**Author:** [@anderson](https://sierraconnect.protoexpress.com/u/anderson)\ **Replies:** 5\ **Last updated:** [July 17, 2026, 3:08pm UTC](https://sierraconnect.protoexpress.com/t/why-do-impedance-mismatches-cause-signal-reflections-on-pcb-transmission-lines/4233 "2026-07-17T15:08:12Z")
I understand that an impedance mismatch causes part of a signal to be reflected back toward the source, but the physical mechanism behind it isn’t clear to me. The case I keep coming back to is series termination at the… --- ## [MIL-Spec Testing Standards Every PCB Engineer Should Know](https://sierraconnect.protoexpress.com/t/mil-spec-testing-standards-every-pcb-engineer-should-know/4244)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [July 14, 2026, 12:13pm UTC](https://sierraconnect.protoexpress.com/t/mil-spec-testing-standards-every-pcb-engineer-should-know/4244 "2026-07-14T12:13:47Z")
Mil-grade PCBs must operate reliably in harsh conditions such as extreme temperatures, humidity, electromagnetic interference (EMI), and mechanical shock. To ensure consistent performance and reliability, the U.S. De… --- ## [How to Evaluate VRM Stability in PCBs](https://sierraconnect.protoexpress.com/t/how-to-evaluate-vrm-stability-in-pcbs/4234)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [July 9, 2026, 3:02pm UTC](https://sierraconnect.protoexpress.com/t/how-to-evaluate-vrm-stability-in-pcbs/4234 "2026-07-09T15:02:52Z")
Originally published at: https://www.protoexpress.com/blog/how-to-evaluate-vrm-stability-in-pcbs/ To measure the voltage regulator module (VRM) stability in PCBs, you need a combination of Bode plot analysis, step-lo… --- ## [How do you minimize signal integrity issues caused by vias in high-speed PCB designs?](https://sierraconnect.protoexpress.com/t/how-do-you-minimize-signal-integrity-issues-caused-by-vias-in-high-speed-pcb-designs/4226)
**Author:** [@Zaibahmed\_Mannur](https://sierraconnect.protoexpress.com/u/Zaibahmed_Mannur)\ **Replies:** 2\ **Last updated:** [July 8, 2026, 2:48pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-minimize-signal-integrity-issues-caused-by-vias-in-high-speed-pcb-designs/4226 "2026-07-08T14:48:19Z")
As data rates continue to increase, vias have become a critical part of the signal path rather than just interlayer connections. Every layer transition can introduce impedance discontinuities, reflections, and timing iss… --- ## [Should non-plated holes be covered by solder mask?](https://sierraconnect.protoexpress.com/t/should-non-plated-holes-be-covered-by-solder-mask/4199)
**Author:** [@Olivia](https://sierraconnect.protoexpress.com/u/Olivia)\ **Replies:** 4\ **Last updated:** [July 7, 2026, 4:12pm UTC](https://sierraconnect.protoexpress.com/t/should-non-plated-holes-be-covered-by-solder-mask/4199 "2026-07-07T16:12:50Z")
I understand the purpose of solder mask on PCB copper features, it helps prevent oxidation, reduces the risk of solder bridging, and protects areas that shouldn’t be soldered. However, I’m not sure about non-plated hole… --- ## [Differential Pair Skew at CAN/RS-485 Termination Resistor Junction](https://sierraconnect.protoexpress.com/t/differential-pair-skew-at-can-rs-485-termination-resistor-junction/4211)
**Author:** [@shyammarimuthu123](https://sierraconnect.protoexpress.com/u/shyammarimuthu123)\ **Replies:** 1\ **Last updated:** [July 7, 2026, 9:17am UTC](https://sierraconnect.protoexpress.com/t/differential-pair-skew-at-can-rs-485-termination-resistor-junction/4211 "2026-07-07T09:17:40Z")
Hi everyone, I’m designing a PCB that includes both CAN and RS-485 interfaces. I’ve routed the differential pairs and matched the trace lengths carefully. During the differential pair skew check, I observed that the sk… --- ## [How to Design a High-Power PCB Stack-Up](https://sierraconnect.protoexpress.com/t/how-to-design-a-high-power-pcb-stack-up/4206)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [July 1, 2026, 3:30pm UTC](https://sierraconnect.protoexpress.com/t/how-to-design-a-high-power-pcb-stack-up/4206 "2026-07-01T15:30:25Z")
Originally published at: How to Design a High-Power PCB Stack-Up | Sierra Circuits When you’re working on high-power PCB stack-ups, select the right layer count, place power and ground planes close together, and opti… --- ## [How do you design an RF PCB that's easier to validate?](https://sierraconnect.protoexpress.com/t/how-do-you-design-an-rf-pcb-thats-easier-to-validate/4205)
**Author:** [@milan](https://sierraconnect.protoexpress.com/u/milan)\ **Replies:** 2\ **Last updated:** [July 1, 2026, 2:16pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-design-an-rf-pcb-thats-easier-to-validate/4205 "2026-07-01T14:16:07Z")
Getting good RF performance isn’t just about choosing the right schematic or laminate. Layout decisions made during PCB design directly affect how easy it is to validate the board once it’s fabricated. I wanted to start… --- ## [Splitting a high-current trace across top and bottom layers](https://sierraconnect.protoexpress.com/t/splitting-a-high-current-trace-across-top-and-bottom-layers/4167)
**Author:** [@Olivia](https://sierraconnect.protoexpress.com/u/Olivia)\ **Replies:** 4\ **Last updated:** [June 29, 2026, 3:03pm UTC](https://sierraconnect.protoexpress.com/t/splitting-a-high-current-trace-across-top-and-bottom-layers/4167 "2026-06-29T15:03:26Z")
For a 20 A current path on 1 oz copper, using a 20°C temperature-rise target, an online calculator suggests a trace width of about 24.8 mm. Can that width be effectively split between the top and bottom layers (for exam… --- ## [Role of PCB Trace Current Capacity in Design](https://sierraconnect.protoexpress.com/t/role-of-pcb-trace-current-capacity-in-design/4177)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [June 24, 2026, 2:29pm UTC](https://sierraconnect.protoexpress.com/t/role-of-pcb-trace-current-capacity-in-design/4177 "2026-06-24T14:29:36Z")
Originally published at: Role of PCB Trace Current Capacity in Design | Sierra Circuits The restrictions posed by the PCB trace current capacity are critically important when it comes to PCB design. While the IPC-22… --- ## [Where do the 10°C and 20°C trace temperature rise limits actually come from?](https://sierraconnect.protoexpress.com/t/where-do-the-10-c-and-20-c-trace-temperature-rise-limits-actually-come-from/4141)
**Author:** [@anderson](https://sierraconnect.protoexpress.com/u/anderson)\ **Replies:** 5\ **Last updated:** [June 19, 2026, 3:48pm UTC](https://sierraconnect.protoexpress.com/t/where-do-the-10-c-and-20-c-trace-temperature-rise-limits-actually-come-from/4141 "2026-06-19T15:48:38Z")
When sizing PCB traces for current carrying capacity, designers are often asked to choose an allowable temperature rise, commonly 5°C, 10°C, or 20°C. What is the actual engineering basis for these commonly used limits? … --- ## [11 IPC Standards that Help PCB Designers Build Reliable Prototypes](https://sierraconnect.protoexpress.com/t/11-ipc-standards-that-help-pcb-designers-build-reliable-prototypes/4157)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [June 17, 2026, 4:38pm UTC](https://sierraconnect.protoexpress.com/t/11-ipc-standards-that-help-pcb-designers-build-reliable-prototypes/4157 "2026-06-17T16:38:27Z")
Originally published at: https://www.protoexpress.com/blog/ipc-standards-help-pcb-designers-build-prototypes/ Standards such as IPC-2221, IPC-2152, and IPC-6012 help PCB designers select the right materials, build la… --- ## [How do you approach RF PCB layout to avoid performance issues?](https://sierraconnect.protoexpress.com/t/how-do-you-approach-rf-pcb-layout-to-avoid-performance-issues/4153)
**Author:** [@Zaibahmed\_Mannur](https://sierraconnect.protoexpress.com/u/Zaibahmed_Mannur)\ **Replies:** 3\ **Last updated:** [June 17, 2026, 2:59pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-approach-rf-pcb-layout-to-avoid-performance-issues/4153 "2026-06-17T14:59:45Z")
We often see RF designs that look correct from a schematic perspective but fail to achieve the expected performance after fabrication. In many cases, the issue isn’t the circuit itself; it’s the PCB layout. At RF freque… --- ## [What Kind of PCBs Power Electric Vehicles?](https://sierraconnect.protoexpress.com/t/what-kind-of-pcbs-power-electric-vehicles/4150)
**Author:** [@Pooja\_Mitra](https://sierraconnect.protoexpress.com/u/Pooja_Mitra)\ **Replies:** 0\ **Last updated:** [June 16, 2026, 3:03pm UTC](https://sierraconnect.protoexpress.com/t/what-kind-of-pcbs-power-electric-vehicles/4150 "2026-06-16T15:03:10Z")
Originally published at: What Kind of PCBs Power EVs? | Sierra Circuits Electric vehicles (EVs) use HDI, heavy copper, and insulated metal substrate (IMS) PCBs to support core operations such as battery management an… --- ## [Do you apply DFA principles before releasing your PCB design?](https://sierraconnect.protoexpress.com/t/do-you-apply-dfa-principles-before-releasing-your-pcb-design/4132)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 2\ **Last updated:** [June 10, 2026, 2:33pm UTC](https://sierraconnect.protoexpress.com/t/do-you-apply-dfa-principles-before-releasing-your-pcb-design/4132 "2026-06-10T14:33:00Z")
We often see boards that are electrically sound but still cause major assembly issues, such as component placement errors, solderability problems, inspection difficulties, and high rework rates. Designers spend considera… --- ## [Real-world impact of via stubs](https://sierraconnect.protoexpress.com/t/real-world-impact-of-via-stubs/4095)
**Author:** [@mark](https://sierraconnect.protoexpress.com/u/mark)\ **Replies:** 5\ **Last updated:** [June 9, 2026, 3:19pm UTC](https://sierraconnect.protoexpress.com/t/real-world-impact-of-via-stubs/4095 "2026-06-09T15:19:47Z")
Has anyone measured the impact of via stubs on insertion loss or eye diagrams for multi-gigabit signals? In simulation the effect is obvious, but I’m curious at what stub lengths people have actually seen measurable deg… --- ## [PCB Inspection Methods: AOI vs. AXI vs. FPT](https://sierraconnect.protoexpress.com/t/pcb-inspection-methods-aoi-vs-axi-vs-fpt/4129)
**Author:** [@Mohamed\_Faheemuddin](https://sierraconnect.protoexpress.com/u/Mohamed_Faheemuddin)\ **Replies:** 0\ **Last updated:** [June 9, 2026, 11:44am UTC](https://sierraconnect.protoexpress.com/t/pcb-inspection-methods-aoi-vs-axi-vs-fpt/4129 "2026-06-09T11:44:19Z")
PCB testing is a critical step in ensuring product quality and reliability. As board complexity increases and component packages become smaller, manufacturers rely on advanced techniques to identify defects before pr… --- ## [PCB Stack-Up: Plan, Design, Manufacture and Repeat](https://sierraconnect.protoexpress.com/t/pcb-stack-up-plan-design-manufacture-and-repeat/4118)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [June 5, 2026, 1:44pm UTC](https://sierraconnect.protoexpress.com/t/pcb-stack-up-plan-design-manufacture-and-repeat/4118 "2026-06-05T13:44:56Z")
Originally published at: PCB Stack-Up: Plan, Design, and Manufacture | Sierra Circuits Often ignored, it is important to understand the difference between an HDI stack-up and a standard stack-up. The primary reason b… --- ## [How do you size PCB traces when you have both high-speed and high-current requirements?](https://sierraconnect.protoexpress.com/t/how-do-you-size-pcb-traces-when-you-have-both-high-speed-and-high-current-requirements/4104)
**Author:** [@Sushmitha](https://sierraconnect.protoexpress.com/u/Sushmitha)\ **Replies:** 2\ **Last updated:** [June 3, 2026, 2:22pm UTC](https://sierraconnect.protoexpress.com/t/how-do-you-size-pcb-traces-when-you-have-both-high-speed-and-high-current-requirements/4104 "2026-06-03T14:22:25Z")
We often see designers run into trouble when a single board needs to handle both high-speed signals and significant current, because the two sets of rules pull in opposite directions. High-current paths need wider, thick… --- ## [7 Medical PCB Design Mistakes That Can Cause Device Failure](https://sierraconnect.protoexpress.com/t/7-medical-pcb-design-mistakes-that-can-cause-device-failure/4087)
**Author:** [@lucy.sierracircuits](https://sierraconnect.protoexpress.com/u/lucy.sierracircuits)\ **Replies:** 0\ **Last updated:** [May 27, 2026, 3:43pm UTC](https://sierraconnect.protoexpress.com/t/7-medical-pcb-design-mistakes-that-can-cause-device-failure/4087 "2026-05-27T15:43:24Z")
Originally published at: https://www.protoexpress.com/blog/medical-pcb-design-mistakes-that-can-cause-device-failure/ Medical PCB design mistakes, such as poor stack-up planning and inefficient thermal management, ca… --- ## [How do you validate and optimize RF PCB performance after layout?](https://sierraconnect.protoexpress.com/t/how-do-you-validate-and-optimize-rf-pcb-performance-after-layout/4084)
**Author:** [@PoulomiG](https://sierraconnect.protoexpress.com/u/PoulomiG)\ **Replies:** 2\ **Last updated:** [May 27, 2026, 11:49am UTC](https://sierraconnect.protoexpress.com/t/how-do-you-validate-and-optimize-rf-pcb-performance-after-layout/4084 "2026-05-27T11:49:12Z")
We often see RF boards behave differently in hardware than they did in simulation, especially at higher frequencies where small layout discontinuities begin to affect impedance and signal integrity. In many cases, the sc… [Next page](https://sierraconnect.protoexpress.com/c/design-and-layout/5.md?page=1)